JPH10242362A - リードフレーム、半導体装置及び半導体装置の製造方法 - Google Patents
リードフレーム、半導体装置及び半導体装置の製造方法Info
- Publication number
- JPH10242362A JPH10242362A JP9040402A JP4040297A JPH10242362A JP H10242362 A JPH10242362 A JP H10242362A JP 9040402 A JP9040402 A JP 9040402A JP 4040297 A JP4040297 A JP 4040297A JP H10242362 A JPH10242362 A JP H10242362A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead
- semiconductor device
- support
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040402A JPH10242362A (ja) | 1997-02-25 | 1997-02-25 | リードフレーム、半導体装置及び半導体装置の製造方法 |
| KR1019970013268A KR19980069737A (ko) | 1997-02-25 | 1997-04-10 | 리이드프레임, 반도체장치 및 그 제조방법 |
| CN97110843A CN1192046A (zh) | 1997-02-25 | 1997-04-30 | 引线框、半导体器件及该半导体器件的制造工艺 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040402A JPH10242362A (ja) | 1997-02-25 | 1997-02-25 | リードフレーム、半導体装置及び半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242362A true JPH10242362A (ja) | 1998-09-11 |
| JPH10242362A5 JPH10242362A5 (enExample) | 2004-11-04 |
Family
ID=12579680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9040402A Pending JPH10242362A (ja) | 1997-02-25 | 1997-02-25 | リードフレーム、半導体装置及び半導体装置の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH10242362A (enExample) |
| KR (1) | KR19980069737A (enExample) |
| CN (1) | CN1192046A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006073670A (ja) * | 2004-08-31 | 2006-03-16 | Denso Corp | 集積回路装置 |
| WO2011148540A1 (ja) * | 2010-05-28 | 2011-12-01 | 株式会社アドバンテスト | プローブ構造体、プローブ装置、プローブ構造体の製造方法、および試験装置 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100377346C (zh) * | 2004-12-23 | 2008-03-26 | 旺宏电子股份有限公司 | 封装件 |
| CN118471938B (zh) * | 2024-06-26 | 2025-02-11 | 池州昀钐半导体材料有限公司 | 一种导线框架和封装组件 |
-
1997
- 1997-02-25 JP JP9040402A patent/JPH10242362A/ja active Pending
- 1997-04-10 KR KR1019970013268A patent/KR19980069737A/ko not_active Withdrawn
- 1997-04-30 CN CN97110843A patent/CN1192046A/zh active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006073670A (ja) * | 2004-08-31 | 2006-03-16 | Denso Corp | 集積回路装置 |
| WO2011148540A1 (ja) * | 2010-05-28 | 2011-12-01 | 株式会社アドバンテスト | プローブ構造体、プローブ装置、プローブ構造体の製造方法、および試験装置 |
| JP2011247792A (ja) * | 2010-05-28 | 2011-12-08 | Advantest Corp | プローブ構造体、プローブ装置、プローブ構造体の製造方法、および試験装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1192046A (zh) | 1998-09-02 |
| KR19980069737A (ko) | 1998-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3526788B2 (ja) | 半導体装置の製造方法 | |
| JPH09312375A (ja) | リードフレーム、半導体装置及び半導体装置の製造方法 | |
| JP3062192B1 (ja) | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 | |
| JP3436159B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
| JP3046024B1 (ja) | リ―ドフレ―ムおよびそれを用いた樹脂封止型半導体装置の製造方法 | |
| JPH0815193B2 (ja) | 半導体装置及びこれに用いるリードフレーム | |
| JP2000058735A (ja) | リードフレーム、半導体装置及び半導体装置の製造方法 | |
| JP3072291B1 (ja) | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
| JP3478139B2 (ja) | リードフレームの製造方法 | |
| JPH09307051A (ja) | 樹脂封止型半導体装置及びその製造方法 | |
| US20080073763A1 (en) | Semiconductor device and method of manufacturing the same | |
| JP2000299423A (ja) | リードフレームおよびそれを用いた半導体装置ならびにその製造方法 | |
| JP3430976B2 (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
| JPH1197570A (ja) | 半導体装置およびその製造方法ならびに半導体装置の実装方法 | |
| JPH10242362A (ja) | リードフレーム、半導体装置及び半導体装置の製造方法 | |
| JP3502377B2 (ja) | リードフレーム、樹脂封止型半導体装置及びその製造方法 | |
| US6909179B2 (en) | Lead frame and semiconductor device using the lead frame and method of manufacturing the same | |
| JPH11297917A (ja) | 半導体装置及びその製造方法 | |
| JP4015118B2 (ja) | 半導体装置 | |
| JP3454192B2 (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
| JPH10154768A (ja) | 半導体装置及びその製造方法 | |
| CN223552535U (zh) | 集成电路芯片封装装置 | |
| JP2001077285A (ja) | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 | |
| JP2003007954A (ja) | 樹脂封止型半導体装置の製造方法 | |
| JPH1174302A (ja) | 樹脂封止型半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040727 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040810 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20050315 |