JPH08509842A - 縦型チップ接続のための接触構造 - Google Patents
縦型チップ接続のための接触構造Info
- Publication number
- JPH08509842A JPH08509842A JP6523750A JP52375094A JPH08509842A JP H08509842 A JPH08509842 A JP H08509842A JP 6523750 A JP6523750 A JP 6523750A JP 52375094 A JP52375094 A JP 52375094A JP H08509842 A JPH08509842 A JP H08509842A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- layer
- contact
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 187
- 239000002184 metal Substances 0.000 claims abstract description 187
- 239000004065 semiconductor Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 230000008018 melting Effects 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 131
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 11
- 239000011247 coating layer Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001010 compromised effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000277331 Salmonidae Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.他の半導体デバイスと縦型に接続するための接触構造と、上面に層構造を持 つ基板(15)とを備え、この基板(15)を上面に対して垂直方向に貫通する 少なくとも1つの金属ピン(8)が設けられ、この金属ピン(8)が半導体物質 からなる少なくとも1つの接続層或いはこの層構造内の金属性導電路(10)又 は金属接触(12)と導電接続され、さらにこの金属ピン(8)が前記上面に対 向する基板(15)の下面を越えて突出し、金属接触(12’)を備えた他の半 導体デバイスがこの下面において前記金属ピン(8)に向けて配列されていると きに、前記金属ピン(8)が他の半導体デバイスの接続のために設けられた金属 接触(12’)と導電接続される半導体デバイス。 2.層構造の上に導電路の融点より低い融点をもつ金属接触(12)が設けられ 、この金属接触(12)が他の半導体デバイスの下面においてその金属ピンと導 電接続される請求項1記載の半導体デバイス。 3.少なくとも1つの金属ピン(8)と少なくとも1つの金属接触(12)が設 けられ、この接触構造をもつ2つの同一構成の半導体デバイスが互いに縦型に配 置され、一方の半導体デバイスの金属ピン(8)が他方の半導体デバイスの金属 接触(12’)と導電接続される請求項2記載の半導体デバイス。 4.基板が酸化物膜(22)であり、半導体デバイスが層構造の上で接着層(1 6)と支持板(17)とにより安定化されている請求項1乃至3の1つに記載の 半導体デバイス。 5.第一の工程で、基板(15;20、21、22)に層構造(1、2、3;2 1、24)がその上面に、金属ピンと接続されるべき半導体物質からなる接触層 或いは導体路又は金属接触が存在する程度に作られ、 第二の工程で、マスクを使用して異方性エッチングプロセスでこの層構造及び基 板が上面から下面に向かって金属ピンが作られる範囲を除去され、 第三の工程で、この範囲に金属が挿入され、 第四の工程で、基板(15;20)の下面が、第三の工程で作られた金属ピン( 8)がこの下面を所定通りに突出するように除去される 請求項1乃至4の1つに記載の半導体デバイスの接触構造の製造方法。 6.第一の工程で、上面に対して同平面に配置された絶縁層(22)によって分 離された2つの半導体物質の層(20、21)からなる基板が使用され、 第二の工程で、金属ピンのために用意された範囲が少なくとも基板の下面を形成 する半導体物質の層(20)にまでエッチングされ、 第四の工程で、この半導体物質の層(20)がその半導体物質が絶縁層(22) に関して選択的にエッチングされることによって完全に除去される 請求項5記載の方法。 7.基板がSOI基板であり、第一の工程で、所定の機能要素がこの基板の薄い シリコン層の中に作られ、次いで全面にわたって第一の誘電体層(25)が析出 され、 第三の工程と第四の工程の聞で、第二の誘電体層(26)が全面に形成されかつ 平坦化され、マスク技術を使用してこの第二の誘電体層(26)に接触ホールと して開口が作られ、この接触ホールが金属で満たされ、その後に第三の誘電体層 (9)に導体路(10)又は金属接触(12)が作られる 請求項6記載の方法。 8.導電路或いは金属接触との接触を形成するための金属ピンが、第二の工程を 、第一の他の工程で誘電体からなる平坦化膜(4)が設けられるように行うこと によって作られ、 第二の他の工程で、マスクを使用して、金属ピンのための範囲が導電路或いは金 属接触の中まで含めてエッチングされ、 第三の他の工程で、このエッチングされた範囲にパッシベーション膜(5)が備 えられ、 第四の他の工程で、、金属ピンのための範囲が完全にエッチングされ、 第五の他の工程で、エッチングされた範囲の側面が誘電体(6)で被膜され、 第六の他の工程で、この誘電体(6)がマスク(7)を使用して導電路或いは金 属接触の範囲で除去される 請求項5乃至7の1つに記載の方法。 9.接触構造の金属ピンを作るための一連の工程が繰り返し層構造の異なる面の 接触を形成するために行われる請求項5乃至8の1つに記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4314913.8 | 1993-05-05 | ||
DE4314913A DE4314913C1 (de) | 1993-05-05 | 1993-05-05 | Verfahren zur Herstellung eines Halbleiterbauelements mit einer Kontaktstrukturierung für vertikale Kontaktierung mit weiteren Halbleiterbauelementen |
PCT/DE1994/000492 WO1994025982A1 (de) | 1993-05-05 | 1994-05-03 | Kontaktstrukturierung für vertikale chipverbindungen |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08509842A true JPH08509842A (ja) | 1996-10-15 |
JP3694021B2 JP3694021B2 (ja) | 2005-09-14 |
Family
ID=6487274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52375094A Expired - Fee Related JP3694021B2 (ja) | 1993-05-05 | 1994-05-03 | 半導体デバイスの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5846879A (ja) |
EP (1) | EP0698289B1 (ja) |
JP (1) | JP3694021B2 (ja) |
KR (1) | KR100323488B1 (ja) |
DE (2) | DE4314913C1 (ja) |
WO (1) | WO1994025982A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006019156A1 (ja) * | 2004-08-20 | 2006-02-23 | Zycube Co., Ltd. | 三次元積層構造を持つ半導体装置の製造方法 |
JP2008098641A (ja) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nandフラッシュメモリー装置及びその製造方法 |
JP2019140162A (ja) * | 2018-02-07 | 2019-08-22 | 株式会社岡本工作機械製作所 | 半導体装置の製造方法 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4433845A1 (de) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
DE4433833A1 (de) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung unter Erreichung hoher Systemausbeuten |
DE19516487C1 (de) * | 1995-05-05 | 1996-07-25 | Fraunhofer Ges Forschung | Verfahren zur vertikalen Integration mikroelektronischer Systeme |
DE19530264A1 (de) * | 1995-08-17 | 1997-02-20 | Abb Management Ag | Leistungshalbleitermodul |
US6498074B2 (en) | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
EP2270845A3 (en) | 1996-10-29 | 2013-04-03 | Invensas Corporation | Integrated circuits and methods for their fabrication |
US6882030B2 (en) | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
US6809421B1 (en) | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
DE19702121C1 (de) * | 1997-01-22 | 1998-06-18 | Siemens Ag | Verfahren zur Herstellung von vertikalen Chipverbindungen |
DE19746642C2 (de) * | 1997-10-22 | 2002-07-18 | Fraunhofer Ges Forschung | Verfahren zur Herstellung eines Halbleiterbauelements sowie dessen Verwendung in einer Chipkarte |
DE19748666C2 (de) * | 1997-11-04 | 2002-08-29 | Fraunhofer Ges Forschung | Verdrahtungsverfahren für mikroelektronische Systeme zur Verhinderung von Produktpiraterie und Produktmanipulation, durch das Verfahren hergestelltes mikroelektronisches System und Verwendung des mikroelektronischen Systems in einer Chipkarte |
DE19813239C1 (de) * | 1998-03-26 | 1999-12-23 | Fraunhofer Ges Forschung | Verdrahtungsverfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur und vertikale integrierte Schaltungsstruktur |
US5989994A (en) * | 1998-12-29 | 1999-11-23 | Advantest Corp. | Method for producing contact structures |
WO2000074134A1 (de) * | 1999-05-27 | 2000-12-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur vertikalen integration von elektrischen bauelementen mittels rückseitenkontaktierung |
DE50005564D1 (de) * | 2000-01-11 | 2004-04-08 | Infineon Technologies Ag | Chipkartenanordnung |
JP3440057B2 (ja) * | 2000-07-05 | 2003-08-25 | 唯知 須賀 | 半導体装置およびその製造方法 |
JP3822043B2 (ja) * | 2000-09-25 | 2006-09-13 | 太陽誘電株式会社 | チップ部品組立体の製造方法 |
US6717254B2 (en) | 2001-02-22 | 2004-04-06 | Tru-Si Technologies, Inc. | Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture |
JP3788268B2 (ja) * | 2001-05-14 | 2006-06-21 | ソニー株式会社 | 半導体装置の製造方法 |
US6787916B2 (en) | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
US6897148B2 (en) | 2003-04-09 | 2005-05-24 | Tru-Si Technologies, Inc. | Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby |
DE10351201B3 (de) * | 2003-11-03 | 2005-07-14 | Infineon Technologies Ag | Sensorvorrichtung mit Waferbondverbindungsaufbau und Herstellungsverfahren derselben |
JP5052130B2 (ja) * | 2004-06-04 | 2012-10-17 | カミヤチョウ アイピー ホールディングス | 三次元積層構造を持つ半導体装置及びその製造方法 |
US7510928B2 (en) * | 2006-05-05 | 2009-03-31 | Tru-Si Technologies, Inc. | Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques |
US20080157405A1 (en) * | 2007-01-03 | 2008-07-03 | International Business Machines Corporation | Chip stack with precision alignment, high yield assembly and thermal conductivity |
DE102007044685B3 (de) * | 2007-09-19 | 2009-04-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Elektronisches System und Verfahren zur Herstellung eines dreidimensionalen elektronischen Systems |
KR101374338B1 (ko) * | 2007-11-14 | 2014-03-14 | 삼성전자주식회사 | 관통 전극을 갖는 반도체 장치 및 그 제조방법 |
DE102009049102B4 (de) | 2009-10-13 | 2012-10-04 | Austriamicrosystems Ag | Halbleiterbauelement mit Durchkontaktierung und Verfahren zur Herstellung einer Durchkontaktierung in einem Halbleiterbauelement |
KR101398080B1 (ko) | 2010-02-04 | 2014-05-23 | 소이텍 | 접합 반도체 구조물 및 그 형성방법 |
US9070851B2 (en) | 2010-09-24 | 2015-06-30 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
US8642456B2 (en) * | 2012-04-18 | 2014-02-04 | International Business Machines Corporation | Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies |
CN205944139U (zh) | 2016-03-30 | 2017-02-08 | 首尔伟傲世有限公司 | 紫外线发光二极管封装件以及包含此的发光二极管模块 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394712A (en) * | 1981-03-18 | 1983-07-19 | General Electric Company | Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers |
KR900008647B1 (ko) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | 3차원 집적회로와 그의 제조방법 |
JPH07112041B2 (ja) * | 1986-12-03 | 1995-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
GB9018766D0 (en) * | 1990-08-28 | 1990-10-10 | Lsi Logic Europ | Stacking of integrated circuits |
EP0516866A1 (en) * | 1991-05-03 | 1992-12-09 | International Business Machines Corporation | Modular multilayer interwiring structure |
AU5835794A (en) * | 1992-08-20 | 1994-03-15 | David A. Capps | Semiconductor wafer for lamination applications |
JPH07221104A (ja) * | 1994-01-28 | 1995-08-18 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置及び電極ピン形成用マスク及び電極ピン形成用マスクを用いた試験方法 |
-
1993
- 1993-05-05 DE DE4314913A patent/DE4314913C1/de not_active Expired - Fee Related
-
1994
- 1994-05-03 JP JP52375094A patent/JP3694021B2/ja not_active Expired - Fee Related
- 1994-05-03 US US08/545,647 patent/US5846879A/en not_active Expired - Lifetime
- 1994-05-03 WO PCT/DE1994/000492 patent/WO1994025982A1/de active IP Right Grant
- 1994-05-03 DE DE59409460T patent/DE59409460D1/de not_active Expired - Lifetime
- 1994-05-03 EP EP94913490A patent/EP0698289B1/de not_active Expired - Lifetime
- 1994-05-03 KR KR1019950704886A patent/KR100323488B1/ko not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006019156A1 (ja) * | 2004-08-20 | 2006-02-23 | Zycube Co., Ltd. | 三次元積層構造を持つ半導体装置の製造方法 |
US7906363B2 (en) | 2004-08-20 | 2011-03-15 | Zycube Co., Ltd. | Method of fabricating semiconductor device having three-dimensional stacked structure |
JP2008098641A (ja) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nandフラッシュメモリー装置及びその製造方法 |
JP2019140162A (ja) * | 2018-02-07 | 2019-08-22 | 株式会社岡本工作機械製作所 | 半導体装置の製造方法 |
TWI825071B (zh) * | 2018-02-07 | 2023-12-11 | 日商岡本工作機械製作所股份有限公司 | 半導體裝置的製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR960702176A (ko) | 1996-03-28 |
DE4314913C1 (de) | 1994-08-25 |
JP3694021B2 (ja) | 2005-09-14 |
KR100323488B1 (ko) | 2002-06-20 |
EP0698289B1 (de) | 2000-07-26 |
US5846879A (en) | 1998-12-08 |
WO1994025982A1 (de) | 1994-11-10 |
EP0698289A1 (de) | 1996-02-28 |
DE59409460D1 (de) | 2000-08-31 |
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