JPH07235680A - 薄膜トランジスタの製造方法 - Google Patents
薄膜トランジスタの製造方法Info
- Publication number
- JPH07235680A JPH07235680A JP2580094A JP2580094A JPH07235680A JP H07235680 A JPH07235680 A JP H07235680A JP 2580094 A JP2580094 A JP 2580094A JP 2580094 A JP2580094 A JP 2580094A JP H07235680 A JPH07235680 A JP H07235680A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- region
- etching
- resist
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000010409 thin film Substances 0.000 title description 7
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 229920001721 polyimide Polymers 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- -1 Phosphorus ions Chemical class 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
電流のTFTを提供する。 【構成】 多結晶シリコンをチャネルに有するトップゲ
ート型薄膜トランジスタにおいて、ソース・ドレイン領
域にイントリンシック領域、低不純物濃度領域、高不純
物濃度領域を有する薄膜トランジスタをゲート電極を同
一のマスクを用いて、2回のエッチング工程と、1回の
不純物注入工程で形成する薄膜トランジスタの製造方
法。
Description
方法に関する。
示デバイスは、表示部の薄型化が可能であり、事務機器
やコンピュータ等の表示装置あるいは特殊な表示装置へ
の用途として要求が高まっている。
・シリコン(a−Si)または結晶を持ったシリコン
(ポリシリコン:poly−Si)を用いた薄膜トラン
ジスタ(TFT)をスイッチング素子としてマトリック
ス上に配した液晶表示装置(TFT−LCD)は、表示
品位が高く、低消費電力であるため、その開発が盛んに
行われている。
−SiTFTよりも移動度が10から100倍程度高
く、その利点を利用して画素スイッチング素子して用い
るだけでなく、周辺駆動回路にpoly−SiTFTを
用いて、画素TFTと駆動回路TFTを同一基板上に同
時に形成する駆動回路一体型TFT−LCDの研究開発
が盛んに行われている。
に比べ移動度は高いが、他方リーク電流(TFTがOF
Fのとき流れてしまうリーク電流)がa−SiTFTに
比べ高いという難点がある。駆動回路を構成する場合に
は、特に問題にならないが画素スイッチングに用いた場
合は、画質劣化の原因となる。
FTには、さまざまに構造上に工夫をこらしたものがあ
る。その一例として、オフセット構造を持ったTFTを
製造する場合、ソースドレイン領域、オフセット領域を
形成するために、フォトリソグラフィー工程が2回必要
である。従って露光のために少くとも2つのマスクが必
要であり、それに共うPEP工程等の露光工程も夫々必
要となり、工程が煩雑化するという問題があった。
の製造方法は、リーク電流の低減化に有利なオフセット
構造を有するものの、少くとも2つのマスクを必要とす
る2回の露光工程が必要で工程が煩雑化する問題があっ
た。
で、1回の露光工程でオフセット構造を形成でき、製造
工程数を簡略化した薄膜トランジスタの製造方法の提供
を目的とする。
に、本発明は絶縁基板上に半導体層を形成する工程と、
この半導体層上に底面が広がったゲート電極を形成する
工程と、このゲート電極をマスクとして前記半導体層に
不純物を導入しソース・ドレイン領域を形成する工程
と、前記ゲート電極の側面をエッチングする工程とを具
備することを特徴とする薄膜トランジスタの製造方法を
提供するものである。ここで、半導体はIV族半導体やII
I-VI族等の化合物半導体であっても良いが、液晶表示装
置に使用した際の画質向上面からシリコンが好ましい。
する際、ゲート電極のエッチング工程、不純物注入工
程、再エッチング工程を、同一のマスクで行うことによ
り、サブミクロンあるいはミクロンオーダのオフセット
領域の製造工程を簡略化することができる。それにより
コストの低下、歩留まりの向上が可能となる。
明する。 (実施例1)実施例1を図1に従い説明する。図1には
nチャネルコプラナ型TFTの製造工程を示している。
光性絶縁基板101上にCVD法によりバッファ層とな
るSiOx膜102を100nm程度被着する。さらに
CVD法によりa−Si:H膜を50nm被着し、45
0度で1時間炉アニールを行った後、例えばXeClエ
キシマレーザアニールによりa−Si:H膜を溶融再結
晶化させpoly−Si膜103を形成する。その後、
フォトリソグラフィ等によりpoly−Si膜103を
パターニング、エッチングし、島状に加工する(図1
(a) )。
SiOx膜104を100nm被着した後、ゲート電極
として例えば燐ドープa−Si膜105を400nm被
着する(図1(b) )。
性ポリイミド106等をパターニングした後に、ゲート
電極107aを例えばCDE法等によりθ1 =25°の
角度がつくようにエッチングを行う(図1(c) )。
ず、イオン注入、イオンドーピング法により燐を注入す
る。イオン注入法の場合、例えば加速電圧は100ke
V、ドーズ量は5×1015cm-2とする。燐イオンは上
部にゲート電極が存在しないソース・ドレイン領域10
8には燐イオンがヘビードープされる。この領域に電気
的に隣接してゲートテーパ端部を通過して燐イオンが注
入される領域、つまりライトリィドープされた領域10
9、さらに隣接して膜厚が215nm以上あるテーパ部
直下の活性層領域、すなわちイントリンシックSiのま
まである領域110が得られる(図1(d) )。
ず、CDE法によるエッチング時に用いたままの状態で
さらに、RIE法の異方性エッチング時のマスクとして
使用する。RIE法によりθ2 =87度のテーパ角でゲ
ート電極を再エッチングすると約600nmのオフセッ
ト領域110と、約460nmのLDD領域109が形
成できる。このときの活性層及びゲート電極の状態につ
いて記載する。ゲート電極の再エッチングによりゲート
電極107b長は短くなり、それにともないチャネル領
域はやや短くなる。チャネルに隣接して前記ライトリィ
ドープ(LDD)領域109、イントリンシックSi領
域(オフセット領域)110がソース・ドレイン領域の
一部として加わる(図1(e) )。
CVD法により層間絶縁膜111を400nm程度被着
する(図1(f) )。次に、例えばXeClエキシマレー
ザアニールによりソース・ドレイン領域、ゲート電極1
07bの活性化を行う。この時のレーザエネルギーは約
200mJ/cm2 とすれば、十分に活性化ができる。
レーザ活性化法を用いた場合不純物の拡散長は、たかだ
か60nm程度であるので約540nm(0.5μm)
のオフセット領域110が形成される。さらに、LDD
領域109とオフセット領域110を同時に溶融させる
ために、良好なn/i接合を形成できることも、リーク
電流低減に寄与している(図1(g) )。
クトホールHを開孔し(図1(h) )、ソース・ドレイン
電極として例えばAl膜をスパッタリング法により成膜
する。フォトリソグラフィ等によりソース・ドレイン電
極112にパターニングして、nチャネルコプラナ型T
FTが完成する(図1(i) )。
ーパー加工について説明を加える。ゲート電極をテーパ
エッチングする際、図2に示したようにゲート電極10
7aのテーパ角をθ1 度とする。次に、レジスト等の剥
離を行わずそのままゲート電極107aをマスクとして
不純物を注入する。さらに、前記ゲート電極107aエ
ッチング時に用いたレジスト等をマスクとし、ゲート電
極107aのエッヂ部が垂直あるいは垂直に近い角度
(θ2 )になるように再エッチングを行ってゲート電極
107bを形成する。この時、θ2 >θ1 なる条件でエ
ッチングすることは、言うまでもない。ゲート電極10
7a、ゲート絶縁膜104を通過して不純物が注入され
る領域の長さ(L1 )と、チャネル領域に隣接したイン
トリンシックポリシリコンのいわゆるオフセット領域の
長さ(L0 )の制御は、ゲート電極107a、107b
の膜厚、イオン加速電圧、ゲート電極テーパ部の角度
(θ1 、θ2 )等によって制御する。この時の活性層1
03中の平均不純物密度を図3に示す。このように、1
度の不純物注入工程で、ゲート電極端107bからの距
離により、高不純物濃度領域108(>L1 )、低不純
物濃度領域109(L1 >L0 )、オフセット領域11
0(L0 >0)の3領域を形成することができる。
1 )で2回でエッチングした後、ゲート電極をマスクと
して、さらに不純物を低濃度で注入するとLDD構造を
とることもできる。
i領域(オフセット領域)104の長さ(L1 )と、低
不純物濃度領域105の長さ(L0 )の比(L1 /L
0 )が0.1以上であることが高い信頼性を得ることか
ら好ましい。
形成するために新たなマスクを必要としない。従ってそ
の分の余分のPEP工程等がなくなり、大幅に工程を簡
略化することができる。
ット構造を形成することができリーク電流を7×10
-11 A程度に低減でき、ゲート電極にテーパがついてい
るにも関わらず、前記ゲート電極直下のゲート絶縁膜中
に燐イオンが注入されずTFTの信頼性が向上する。 (実施例2)本実施例が、実施例1と異なる点は、半導
体がSi以外の半導体である化合物半導体のGaAsで
あり、ゲート電極がWNxのショットキー電極になった
ことにある。この場合、実施例1の様なゲート絶縁膜は
必要ないので、Si基板上にGaAs層を形成してお
き、このGaAs層上にさらに形成したテーパ形状(底
面が広がった台形)のゲート電極から不純物をイオン注
入してソース・ドレイン領域を形成し、この後、ゲート
電極の側面を実施例1と同様にエッチングする。エッチ
ングした下部のGaAs層がオフセット領域となる。こ
れによって実施例1とは材料系は異なるもののGaAs
を用いたコプラナ型TFTをオフセット領域を持った構
造で実施例1と同様に形成することができる。甲第1号
証かについても、実施例1と同様に奏する事ができる。
いて説明したが、本発明の主旨を逸脱しない範囲におい
て、さまざまに変形することができる。例えばソース・
ドレイン領域、チャネル領域よりもゲート電極が上にく
るTFT、例えばスタガ型TFTについても同様に実施
することができる。また、nチャネルまたはpチャネル
タイプのTFTに適用することができるのは言うまでも
ない。ゲート電極材料については、高融点金属、その経
過物、窒化物などが使用でき、また、ゲート絶縁膜につ
いては、窒化シリコン、窒化酸化シリコン等が使用で
き、さらには、ソース・ドレイン領域、チャネル領域に
ついては、、多結晶、非晶質の各種半導体を使用するこ
とができる。
るためのフォトリソグラフィ工程を削除し、製造工程を
簡略化することができる。それによりコストの低下、歩
留まりの向上が可能となる。
Claims (1)
- 【請求項1】絶縁基板上に半導体層を形成する工程と、
この半導体層上に底面が広がったゲート電極を形成する
工程と、このゲート電極をマスクとして前記半導体層に
不純物を導入しソース・ドレイン領域形成する工程と、
前記ゲート電極の側面をエッチングする工程とを具備す
ることを特徴とする薄膜トランジスタの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02580094A JP3398453B2 (ja) | 1994-02-24 | 1994-02-24 | 薄膜トランジスタの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02580094A JP3398453B2 (ja) | 1994-02-24 | 1994-02-24 | 薄膜トランジスタの製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001047724A Division JP3398665B2 (ja) | 2001-02-23 | 2001-02-23 | 薄膜トランジスタの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07235680A true JPH07235680A (ja) | 1995-09-05 |
JP3398453B2 JP3398453B2 (ja) | 2003-04-21 |
Family
ID=12175934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP02580094A Expired - Fee Related JP3398453B2 (ja) | 1994-02-24 | 1994-02-24 | 薄膜トランジスタの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3398453B2 (ja) |
Cited By (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09116161A (ja) * | 1995-10-18 | 1997-05-02 | Seiko Epson Corp | 薄膜半導体装置およびその製造方法 |
JP2001007110A (ja) * | 1999-06-22 | 2001-01-12 | Semiconductor Energy Lab Co Ltd | 配線材料およびこれを用いた配線を備えた半導体装置およびその作製方法 |
US6335290B1 (en) | 1998-07-31 | 2002-01-01 | Fujitsu Limited | Etching method, thin film transistor matrix substrate, and its manufacture |
JP2002014337A (ja) * | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP2002064207A (ja) * | 2000-06-05 | 2002-02-28 | Semiconductor Energy Lab Co Ltd | 発光装置の作製方法 |
JP2002175028A (ja) * | 2000-07-31 | 2002-06-21 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP2002203862A (ja) * | 2000-10-26 | 2002-07-19 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
US6515336B1 (en) | 1999-09-17 | 2003-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors having tapered gate electrode and taped insulating film |
US6541294B1 (en) | 1999-07-22 | 2003-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US6596571B2 (en) | 2000-06-07 | 2003-07-22 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
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