JPH07169265A - 同期式ランダムアクセスメモリ装置 - Google Patents

同期式ランダムアクセスメモリ装置

Info

Publication number
JPH07169265A
JPH07169265A JP6274089A JP27408994A JPH07169265A JP H07169265 A JPH07169265 A JP H07169265A JP 6274089 A JP6274089 A JP 6274089A JP 27408994 A JP27408994 A JP 27408994A JP H07169265 A JPH07169265 A JP H07169265A
Authority
JP
Japan
Prior art keywords
counter
signal
burst
address
burst mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6274089A
Other languages
English (en)
Japanese (ja)
Inventor
Hee-Choul Park
煕哲 朴
Kook-Hwan Kweon
國煥 權
Jeon-Taek Im
田澤 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH07169265A publication Critical patent/JPH07169265A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Dram (AREA)
JP6274089A 1993-11-08 1994-11-08 同期式ランダムアクセスメモリ装置 Pending JPH07169265A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1993P23603 1993-11-08
KR1019930023603A KR100309800B1 (ko) 1993-11-08 1993-11-08 동기랜덤액세스메모리장치

Publications (1)

Publication Number Publication Date
JPH07169265A true JPH07169265A (ja) 1995-07-04

Family

ID=19367541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6274089A Pending JPH07169265A (ja) 1993-11-08 1994-11-08 同期式ランダムアクセスメモリ装置

Country Status (4)

Country Link
US (1) US5610874A (enExample)
JP (1) JPH07169265A (enExample)
KR (1) KR100309800B1 (enExample)
TW (1) TW308691B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0991954A (ja) * 1995-09-19 1997-04-04 Nec Corp 半導体記憶装置
WO1999067788A1 (fr) * 1998-06-25 1999-12-29 Seiko Epson Corporation Dispositif memoire a semi-conducteur

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2907074B2 (ja) * 1995-08-25 1999-06-21 日本電気株式会社 半導体記憶装置
KR0164805B1 (ko) * 1995-12-22 1999-02-01 김광호 버스트 모드를 지원하는 내부 컬럼 어드레스 발생 회로
JP3247603B2 (ja) * 1996-02-05 2002-01-21 インターナショナル・ビジネス・マシーンズ・コーポレーション プレデコーダ回路及びデコーダ回路
KR100218734B1 (ko) * 1996-05-06 1999-09-01 김영환 싱크로노스 메모리의 내부펄스 신호발생 방법 및 그장치
US6009038A (en) * 1996-05-31 1999-12-28 United Microelectronics Corporation Addressing unit
JPH09320269A (ja) * 1996-05-31 1997-12-12 Nippon Steel Corp アドレス装置
KR100301036B1 (ko) 1997-06-26 2001-09-03 윤종용 데이터입출력마스크입력버퍼의전류소모를감소시키기위한제어부를구비하는동기식반도체메모리장치
US5973993A (en) 1998-02-27 1999-10-26 Micron Technology, Inc. Semiconductor memory burst length count determination detector
US6130853A (en) * 1998-03-30 2000-10-10 Etron Technology, Inc. Address decoding scheme for DDR memory
US6049505A (en) 1998-05-22 2000-04-11 Micron Technology, Inc. Method and apparatus for generating memory addresses for testing memory devices
JP3942332B2 (ja) * 2000-01-07 2007-07-11 富士通株式会社 半導体記憶装置
US7143257B2 (en) * 2003-10-14 2006-11-28 Atmel Corporation Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
KR100546418B1 (ko) * 2004-07-27 2006-01-26 삼성전자주식회사 데이터 출력시 ｄｄｒ 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법
US7257045B2 (en) * 2005-11-28 2007-08-14 Advanced Micro Devices, Inc. Uni-stage delay speculative address decoder

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
US5077693A (en) * 1990-08-06 1991-12-31 Motorola, Inc. Dynamic random access memory
JP3992757B2 (ja) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム
JPH05266685A (ja) * 1992-03-24 1993-10-15 Sharp Corp 記憶装置
US5392239A (en) * 1993-05-06 1995-02-21 S3, Incorporated Burst-mode DRAM

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0991954A (ja) * 1995-09-19 1997-04-04 Nec Corp 半導体記憶装置
US6038648A (en) * 1995-09-19 2000-03-14 Nec Corporation Semiconductor memory device having the same access timing over clock cycles
WO1999067788A1 (fr) * 1998-06-25 1999-12-29 Seiko Epson Corporation Dispositif memoire a semi-conducteur
US6341096B1 (en) 1998-06-25 2002-01-22 Seiko Epson Corporation Semiconductor memory device

Also Published As

Publication number Publication date
US5610874A (en) 1997-03-11
KR950015367A (ko) 1995-06-16
KR100309800B1 (ko) 2001-12-15
TW308691B (enExample) 1997-06-21

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