JPH07162281A - データ入力バッファ - Google Patents

データ入力バッファ

Info

Publication number
JPH07162281A
JPH07162281A JP6243203A JP24320394A JPH07162281A JP H07162281 A JPH07162281 A JP H07162281A JP 6243203 A JP6243203 A JP 6243203A JP 24320394 A JP24320394 A JP 24320394A JP H07162281 A JPH07162281 A JP H07162281A
Authority
JP
Japan
Prior art keywords
transistor
power supply
supply voltage
level
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6243203A
Other languages
English (en)
Japanese (ja)
Inventor
Kyung-Woo Kang
京雨 姜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH07162281A publication Critical patent/JPH07162281A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
JP6243203A 1993-10-06 1994-10-06 データ入力バッファ Pending JPH07162281A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019930020596A KR0126254B1 (ko) 1993-10-06 1993-10-06 반도체 메모리 장치의 데이터 입력 버퍼
KR1993P20596 1993-10-06

Publications (1)

Publication Number Publication Date
JPH07162281A true JPH07162281A (ja) 1995-06-23

Family

ID=19365299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6243203A Pending JPH07162281A (ja) 1993-10-06 1994-10-06 データ入力バッファ

Country Status (4)

Country Link
JP (1) JPH07162281A (ko)
KR (1) KR0126254B1 (ko)
DE (1) DE4435649B4 (ko)
TW (1) TW357351B (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9929724B2 (en) 2015-02-13 2018-03-27 Samsung Electronics Co., Ltd. Schmitt trigger circuit and non-volatile memory device including the same
CN109036323A (zh) * 2018-09-26 2018-12-18 北京集创北方科技股份有限公司 输出级电路、控制方法、驱动装置以及显示装置
CN109036322A (zh) * 2018-09-26 2018-12-18 北京集创北方科技股份有限公司 输入缓冲器、控制方法、驱动装置以及显示装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100670683B1 (ko) * 2005-03-31 2007-01-17 주식회사 하이닉스반도체 반도체 소자의 데이터 입력 버퍼
TWI762317B (zh) 2021-05-17 2022-04-21 力晶積成電子製造股份有限公司 感測電路以及測試裝置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
US4783607A (en) * 1986-11-05 1988-11-08 Xilinx, Inc. TTL/CMOS compatible input buffer with Schmitt trigger

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9929724B2 (en) 2015-02-13 2018-03-27 Samsung Electronics Co., Ltd. Schmitt trigger circuit and non-volatile memory device including the same
CN109036323A (zh) * 2018-09-26 2018-12-18 北京集创北方科技股份有限公司 输出级电路、控制方法、驱动装置以及显示装置
CN109036322A (zh) * 2018-09-26 2018-12-18 北京集创北方科技股份有限公司 输入缓冲器、控制方法、驱动装置以及显示装置
CN109036322B (zh) * 2018-09-26 2023-11-03 北京集创北方科技股份有限公司 输入缓冲器、控制方法、驱动装置以及显示装置
CN109036323B (zh) * 2018-09-26 2023-11-03 北京集创北方科技股份有限公司 输出级电路、控制方法、驱动装置以及显示装置

Also Published As

Publication number Publication date
KR950012703A (ko) 1995-05-16
KR0126254B1 (ko) 1998-04-10
DE4435649A1 (de) 1995-04-13
TW357351B (en) 1999-05-01
DE4435649B4 (de) 2005-08-25

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