JPH069152U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH069152U
JPH069152U JP046162U JP4616292U JPH069152U JP H069152 U JPH069152 U JP H069152U JP 046162 U JP046162 U JP 046162U JP 4616292 U JP4616292 U JP 4616292U JP H069152 U JPH069152 U JP H069152U
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor element
semiconductor device
bonding
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP046162U
Other languages
English (en)
Inventor
友広 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP046162U priority Critical patent/JPH069152U/ja
Publication of JPH069152U publication Critical patent/JPH069152U/ja
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 半導体装置において、ボンディングワイヤど
うしの接触に起因するデバイス不良を防止させる。 【構成】 リードフレーム１上に搭載される半導体素子
３と、前記リードフレーム１の端部に形成される外部と
の接続用端子４と、前記半導体素子３の電極と前記接続
用端子４とを電気的に接続するボンディングワイヤ５と
を有し、少なくとも、前記半導体素子３及びボンディン
グワイヤ５が樹脂封止されて成る半導体装置において、
前記リードフレーム１上に絶縁物６を介して搭載される
ボンディングパッド７を形成することを特徴とする。

Description

【考案の詳細な説明】
【０００１】
【産業上の利用分野】
本考案は、リードフレーム上に配置された半導体素子が樹脂封止されてなる半 導体装置に関する。
【０００２】
【従来の技術】
従来例による半導体装置について図３、図４及び図５に従って説明する。図３ は従来例であるリードフレームを利用した半導体装置の構造図であり、図４は図 ３に示す従来例におけるリードフレームの断面図（ａ）及び平面図（ｂ）であり 、図５は図３の構造のものを絶縁樹脂により封止した半導体装置の断面図（ａ） 及び平面図（ｂ）出ある。
【０００３】 図３に示すように、銅材等のリードフレーム１上に絶縁ペースト２を介して搭 載される半導体素子３と前記リードフレーム１の端部に外部との接続用端子４を 形成し、前記半導体素子３と前記接続端子４とがボンディングワイヤ５により電 気的に接続され、図５に示すように、絶縁樹脂８により封止する。
【０００４】
【考案が解決しようとする課題】
従来の半導体装置において、前記半導体装置の端子配置及び半導体素子の電極 配置等により、半導体素子と接続用端子とをボンディングワイヤにより接続する 際に、ボンディングワイヤどうしが交差しなければならない場合に、絶縁樹脂封 止を行なう時に樹脂の流れる圧力によりボンディングワイヤが流れ、ボンディン グワイヤどうしが接触し、デバイス不良となる可能性がある。
【０００５】 本考案は、上記問題点を解決することを目的とするものである。
【０００６】
【課題を解決するための手段】
リードフレーム上に搭載される半導体素子と、前記リードフレームの端部に形 成される外部との接続用端子と、前記半導体素子の電極と前記接続用端子とを電 気的に接続するボンディングワイヤとを有し、少なくとも、前記半導体素子及び ボンディングワイヤが樹脂封止されて成る半導体装置において、前記リードフレ ーム上に絶縁物を介して搭載されるボンディングパッドを設けたことを特徴とす る。
【０００７】
【作用】
リードフレーム上に絶縁物を介して搭載されるボンディングパッドを設けたこ とにより、交差するボンディングワイヤの一方を半導体素子の電極から上記ボン ディングパッドを経てリードフレームの接続用端子に接続することができ、ボン ディングワイヤどうしの交差をなくすことができる。このため、絶縁樹脂封止を 行なう際に樹脂の流れる圧力によりボンディングワイヤが流れ、ボンディングワ イヤどうしが接触することによるデバイス不良を防ぐことができる。
【０００８】
【実施例】
本考案の一実施例を図１及び図２に従って説明する。図１は本実施例によるリ ードフレームを利用した半導体装置の構造を説明する図であり、図２は図１の実 施例に示すリードフレームの断面図（ａ）及び平面図（ｂ）である。
【０００９】 図１に示すように、リードフレーム１上に絶縁ペースト２を介して搭載される 半導体素子３と、前記リードフレーム１の端部に外部との接続用端子４を形成し 、前記半導体素子３と接続用端子４とをボンディングワイヤ５により電気的に接 続する。この際に、交差するボンディングワイヤ５の一方を前記リードフレーム １上に絶縁物６を介して搭載されるボンディングパッド７を経て接続用端子４と 接続することにより、ボンディングワイヤ５どうしの交差をなくすことができる 。また、絶縁樹脂封止（図示せず）を行う際に、樹脂の流れる圧力によりボンデ ィングワイヤ５が流れ、ボンディングワイヤ５どうしが接触することを防ぐこと ができる。
【００１０】 尚、交差するボンディングワイヤの組が２以上の場合は、前記ボンディングパ ッドを必要に応じて増加させ、ボンディングワイヤどうしの交差をなくすと良い 。
【００１１】
【考案の効果】
以上のように本考案によれば、半導体装置において、リードフレーム上に絶縁 物を介して搭載されるボンディングパッドを設けたことにより、ボンディングワ イヤどうしの交差をなくすことができる。そして、このことにより、絶縁樹脂封 止を行なう際にボンディングワイヤどうしが接触することによるデバイス不良を 防ぐことができる。
【図面の簡単な説明】
【図１】本考案の一実施例を示す半導体装置の構造を説
明する図である。
【図２】図１に示す実施例におけるリードフレームの断
面図（ａ）及び平面図（ｂ）である。
【図３】従来例の半導体装置の構造を説明する図であ
る。
【図４】図３に示す従来例におけるリードフレームの断
面図（ａ）及び平面図（ｂ）である。
【図５】図３に示す構造に絶縁樹脂封止した断面図
（ａ）及び平面図（ｂ）である。
【符号の説明】
１ リードフレーム ２ 絶縁ペースト ３ 半導体素子 ４ 接続用端子 ５ ボンディングワイヤ ６ 絶縁物 ７ ボンディングパッド ８ 絶縁樹脂

Claims (1)

    【実用新案登録請求の範囲】
  1. 【請求項１】 リードフレーム上に搭載される半導体素
    子と、前記リードフレームの端部に形成される外部との
    接続用端子と、前記半導体素子の電極と前記接続用端子
    とを電気的に接続するボンディングワイヤとを有し、少
    なくとも、前記半導体素子及びボンディングワイヤが樹
    脂封止されて成る半導体装置において、前記リードフレ
    ーム上に絶縁物を介して搭載されるボンディングパッド
    を設けたことを特徴とする半導体装置。
JP046162U 1992-07-02 1992-07-02 半導体装置 Pending JPH069152U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP046162U JPH069152U (ja) 1992-07-02 1992-07-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP046162U JPH069152U (ja) 1992-07-02 1992-07-02 半導体装置

Publications (1)

Publication Number Publication Date
JPH069152U true JPH069152U (ja) 1994-02-04

Family

ID=12739324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP046162U Pending JPH069152U (ja) 1992-07-02 1992-07-02 半導体装置

Country Status (1)

Country Link
JP (1) JPH069152U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088453A (ja) * 2005-09-23 2007-04-05 Freescale Semiconductor Inc スタックダイパッケージを製造する方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088453A (ja) * 2005-09-23 2007-04-05 Freescale Semiconductor Inc スタックダイパッケージを製造する方法

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