JPS61240644A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61240644A
JPS61240644A JP60082757A JP8275785A JPS61240644A JP S61240644 A JPS61240644 A JP S61240644A JP 60082757 A JP60082757 A JP 60082757A JP 8275785 A JP8275785 A JP 8275785A JP S61240644 A JPS61240644 A JP S61240644A
Authority
JP
Japan
Prior art keywords
lead
wirings
island
internal leads
cutout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60082757A
Other languages
English (en)
Inventor
Takumi Matsukura
松倉　巧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60082757A priority Critical patent/JPS61240644A/ja
Publication of JPS61240644A publication Critical patent/JPS61240644A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止半導体装置の
構造、更に詳しくはリードフレームの形状の改良に関す
る。
〔従来の技術〕
たアイランド部２とを一体に形成したリードフレームの
状態で、アイランド部に半導体素子３を接着し、この半
導体素子の電極バッド７と内部ＩＪ−ド１間を金属ワイ
ヤ４でワイヤーボンドした後。
樹脂モールド５で気密封止する。
〔発明が解決しようとする問題点〕
しかし々がら、上述した従来のリードフレーム構造では
金属ワイヤが数十ミクロンの細線のために変形しやすく
、加工工程中に他の部材との不測の接触や、工程間の搬
送による振動、衝撃により、またはモールド時に圧入さ
れる樹脂によって変形を生ずる。すなわち第４図のよう
に金属ワイヤ４が実線で示されるように正常な状態でボ
ンディングが施されても、破線で示すように変形し、隣
接するワイヤ４ａや内部リード１０との接触事故を生ず
る。また、完全な接触に至らない場合でも、接触しやす
い状態であれば電気的に漏洩を生じたり、電気特性が不
安定になるなどの信頼性上の問題がある。電極数が多く
、かつ小型化された半導体装置ではワイヤループ長が長
くなり、たるみが発生する為に特にこの問題が顕著とな
る。
〔問題点を解決するための手段〕
本発明の半導体装置は、半導体素子を搭載するアイラン
ド部と、該アイランド部を取囲むように配置された複数
のメッキの施された内部リードと、前記アイランド部に
搭載された半導体素子と、該半導体素子の電極パッドと
内部リードとを接続した金属ワイヤとを有する半導体装
置において、前記内部リードの先端部が切り込みを有し
該切り込み部を有する先端部は金属ワイヤの接続される
面が互いに向い合う方向に捷けられ、前記金属ワイヤは
前記切り込み都を通して＊、　ｉｔパッドと内部リード
に接続されて構成される。上記構成では内部リードと電
極パッドを接続する金属ワイヤは切り込み部により支持
されるので、金属ワイヤの変形が防止できる。
〔実施例〕
次に、本発明について図面全参照して説明する。
第１図は本発明の一実施例を示す一部概略斜視図であり
、第１図に示すように、内部リード１とそれに囲まれた
アイランド部２とが一体に形成されたリードフレームの
状態で、アイランド部２には半導体素子３が接着されて
いる。また、内部り一部１の先端部には切り込み部６が
形成されており、先端部は内部リードと電極パッドの接
続面が互いに向い合う方向、すなわち上方へ折り曲げた
構造となっている。
この構造において、半導体素子３の電極パッド７と内部
リード１間全金属ワイヤ４で接続するのであるがその際
に金属ワイヤ４は内部リードに形成した切り込み部６全
通してボンディングされることになる。
第２図は第１図に示した本実施例の金属ワイヤ及びその
接続部の断面図である。金属ワイヤ４は第２図に示すよ
うに内部リード１の先端部で支持される為にたるみが防
止され半導体素子３．及びアイランド部２との接触は発
生し々い。また、搬送時の振動や樹脂封入時の圧力等の
水平方向の力に対しても、第３図に示し、たよりに切り
込み部６によって左右方向より支持される為に金属ワイ
ヤは変形しにくく従って隣接する内部リード１ａや金属
ワイヤ４ａとの接触は発生し々い。
〔発明の効果〕
以上説明したように本発明は、金属ワイヤを、内部リー
ド先端九設けられた切り込みによって支持することによ
り、金属ワイヤの変形によるリードとの接触や、金属ワ
イヤ同志の接触による短絡事故が防止でき、これにより
、半導体装置の製造歩留全向上させるとともに、信頼性
も著しく向上させることができる。
【図面の簡単な説明】
第１図は本発明の一実施例の概略斜視図、第２図は第１
図の要部断面図、第３図は本発明の一実施例の平面図、
第４図、第５図、第６図はそれぞれ従来の半導体装置の
平面図、断面図、概略斜視図である。 １．１ａ・・・・・・内部リード、２・・・・・アイラ
ンド部。 ３・・・・・・半導体素子、４，４ａ・・・・・・金属
ワイヤ、５・・・・・・樹脂％６・・・・・・切り込み
部、７・・・・・・電極パッド。 −６＝ １＾０

Claims (1)

    【特許請求の範囲】
  1. 　半導体素子を搭載するアイランド部と、該アイランド
    部を取囲むように配置された複数のメッキの施された内
    部リードと、前記アイランド部に搭載された半導体素子
    と、該半導体素子の電極パッドと内部リードとを接続し
    た金属ワイヤとを有する半導体装置において、前記内部
    リードの先端部が切り込みを有し該切り込み部を有する
    先端部は金属ワイヤの接続される面が互いに向い合う方
    向にまげられ、前記金属ワイヤは前記切り込み部を通し
    て電極パッドと内部リードに接続されていることを特徴
    とする半導体装置。
JP60082757A 1985-04-18 1985-04-18 半導体装置 Pending JPS61240644A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60082757A JPS61240644A (ja) 1985-04-18 1985-04-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60082757A JPS61240644A (ja) 1985-04-18 1985-04-18 半導体装置

Publications (1)

Publication Number Publication Date
JPS61240644A true JPS61240644A (ja) 1986-10-25

Family

ID=13783313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60082757A Pending JPS61240644A (ja) 1985-04-18 1985-04-18 半導体装置

Country Status (1)

Country Link
JP (1) JPS61240644A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163345U (ja) * 1988-05-06 1989-11-14
US5156320A (en) * 1991-02-27 1992-10-20 Kaijo Corporation Wire bonder and wire bonding method
WO2005067041A1 (en) * 2003-08-13 2005-07-21 Tian Siang Yip Wire-bonded integrated circuit package and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163345U (ja) * 1988-05-06 1989-11-14
US5156320A (en) * 1991-02-27 1992-10-20 Kaijo Corporation Wire bonder and wire bonding method
WO2005067041A1 (en) * 2003-08-13 2005-07-21 Tian Siang Yip Wire-bonded integrated circuit package and manufacturing method thereof

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