JPH0362564A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0362564A
JPH0362564A JP1197560A JP19756089A JPH0362564A JP H0362564 A JPH0362564 A JP H0362564A JP 1197560 A JP1197560 A JP 1197560A JP 19756089 A JP19756089 A JP 19756089A JP H0362564 A JPH0362564 A JP H0362564A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
electrode
chip
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1197560A
Other languages
English (en)
Inventor
Yukako Takahashi
由佳子 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP1197560A priority Critical patent/JPH0362564A/ja
Publication of JPH0362564A publication Critical patent/JPH0362564A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にボンディング線を有す
る半導体装置に関する。
〔従来の技術〕
従来の半導体装置は第３図に示すように、アイランド６
の周囲に内部リード２が水平に配列されて設けられ、ア
イランド６の上に半導体チップ１がマウントされ、半導
体チップ１の表面に設けられた電極５と内部リード２の
先端との間をボンディング線３が弧状に接続されていた
。
〔発明が解決しようとする課題〕
上述した従来の半導体装置では、半導体チップ上の電極
とリードがそれぞれ水平面上にあるため、ボンディング
線が弧状に張られ内部リードの先端と半導体チップとの
間でボンディング線が互に接触して電気的に短絡すると
いう問題点がある。
また、大型の半導体チップを小型のパッケージに封止す
る際、内部リードを半導体チップ上に設ける場合がある
が、その時内部リードに加えたボンディング加重が半導
体チップに加わり、クラックや欠けを発生させるという
問題点がある。
〔課題を解決するための手段〕
本発明の半導体装置は、半導体チップと、前記半導体チ
ップの周囲に配置され且つ先端が前記半導体チップの表
面に対して上方に９０”〜１４０°の角度に折り曲げた
内部リードと、前記内部リードと前記半導体チップとの
間を電気的に接続したボンディング線とを有する。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図（ａ）、（ｂ）は本発明の第１の実施例を示す平
面図及びＡ−Ａ’線断面図である。
第１図（ａ）、（ｂ）に示すように、アイランド６の上
に半導体チップ１がマウントされ、アイランド６の周囲
に先端を上方に直角に折り曲げた内部リード２が配列さ
れて設けられ、半導体チップ１の表面に設けられた電極
５と内部リード２の先端との間がボンディング線３で接
続される。ここでボンディング線３の一端は電極５の水
平面に圧着され他端は内部リードの先端の垂直面に圧着
されている。
第２図（ａ）、（ｂ）は本発明の第２の実施例を示す平
面図及びＢ−Ｂ’線断面図である。
第２図（ａ）、（ｂ）に示すように、アイランド６の上
にマウントされた半導体チップｌの表面に設けられた絶
縁膜７の上に先端が上方に１３５°の角度に折曲げられ
た内部リード２が接して設けられ、半導体チップの表面
に設けられた電ｆ！５と内部リード２の先端との間がボ
ンディング線３で電気的に接続される。ここで、内部り
一ド３の先端に加わるボンディング加重が内部り一ド３
の先端の弾性変形により半導体チップｌに与える応力を
減少させ、半導体チップのクラック欠けを防止できる利
点がある。
〔発明の効果〕
以上説明したように本発明は、半導体チップ上の電極と
内部リードとを結ぶボンディング線の圧着面が内部リー
ド上では電極上と９０”〜１４０°の角度を持った状態
でボンディングすることにより、従来のものより線長が
短くなり、ボンディング線のだれ、及び樹脂封止時のボ
ンディング線流れ等による短絡事故を防止できるという
効果を有する。
また、大型の半導体チップを小型のパッケージに封止す
る際、内部リードを半導体チップ上に設ける場合がある
が、その時内部リードのボンディング加重による半導体
チップのクラックや欠は等の発生を防止し、信頼性の高
い半導体装置を実現できるという効果を有する。
【図面の簡単な説明】
第１図（ａ）、（ｂ）は本発明の第１の実施例を示す平
面図及びＡ−Ａ’線断面図、第２図（ａ＞、（ｂ）は本
発明の第２の実施例の平面図及びＢ−Ｂ’線断面図、第
３図は従来の半導体装置の一例を示す斜視図である。 １・・・半導体チップ、２・・・内部リード、３・・・
ボンディング線、５・・・電極、６・・・アイランド、
７・・・絶縁膜。

Claims (1)

    【特許請求の範囲】
  1. 半導体チップと、前記半導体チップの周囲に配置され且
    つ先端が前記半導体チップの表面に対して上方に９０゜
    〜１４０゜の角度に折り曲げた内部リードと、前記内部
    リードと前記半導体チップとの間を電気的に接続したボ
    ンディング線とを有することを特徴とする半導体装置。
JP1197560A 1989-07-28 1989-07-28 半導体装置 Pending JPH0362564A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1197560A JPH0362564A (ja) 1989-07-28 1989-07-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1197560A JPH0362564A (ja) 1989-07-28 1989-07-28 半導体装置

Publications (1)

Publication Number Publication Date
JPH0362564A true JPH0362564A (ja) 1991-03-18

Family

ID=16376530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1197560A Pending JPH0362564A (ja) 1989-07-28 1989-07-28 半導体装置

Country Status (1)

Country Link
JP (1) JPH0362564A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288447B1 (en) * 1999-01-22 2001-09-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a plurality of interconnection layers
JP2014093409A (ja) * 2012-11-02 2014-05-19 Denso Corp 電子装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221549B2 (ja) * 1982-06-15 1987-05-13 Ootsuka Koki Kk
JPH01125964A (ja) * 1987-11-11 1989-05-18 Nec Corp リードフレーム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221549B2 (ja) * 1982-06-15 1987-05-13 Ootsuka Koki Kk
JPH01125964A (ja) * 1987-11-11 1989-05-18 Nec Corp リードフレーム

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288447B1 (en) * 1999-01-22 2001-09-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a plurality of interconnection layers
US6541862B2 (en) 1999-01-22 2003-04-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method
US6835647B2 (en) 1999-01-22 2004-12-28 Renesas Technology Corp. Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method
JP2014093409A (ja) * 2012-11-02 2014-05-19 Denso Corp 電子装置およびその製造方法

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