JPS62183546A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS62183546A
JPS62183546A JP61026286A JP2628686A JPS62183546A JP S62183546 A JPS62183546 A JP S62183546A JP 61026286 A JP61026286 A JP 61026286A JP 2628686 A JP2628686 A JP 2628686A JP S62183546 A JPS62183546 A JP S62183546A
Authority
JP
Japan
Prior art keywords
shape
original form
side face
lead
form body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61026286A
Other languages
English (en)
Inventor
Hiroshi Koyanagi
博 小柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61026286A priority Critical patent/JPS62183546A/ja
Publication of JPS62183546A publication Critical patent/JPS62183546A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子(ベレット)を樹脂などで包んだ
形の半導体装置に関する。
〔従来の技術〕
樹脂封止の従来の半導体装置のリード端子は、帯状の金
属導体によ多形成されているのが一般的である。
〔発明が解決しようとする問題点〕
上述した従来の半導体装置のリード端子は、封止樹脂と
接する界面が連続的な平面となっているので、この平面
を伝わって外部の湿気が封止樹脂内部の半導体素子まで
浸入し、半導体素子の特性を劣化させるという欠点があ
る。
〔問題点を解決するための手段〕
本発明の半導体装置のリード端子は、連続的な平面を少
なくする為、平面上でジグザグなパターンの原形体から
、長さ方向に沿う曲げ線で折シ曲けることにより、前記
平面に沿う封止樹脂体の水平な界面が途中で中断し、そ
の代わシ、垂直な界面に迂回し、また元の水平面に沿う
界面に戻して、外部湿気の浸入径路を複雑にし、耐湿性
を向上させている。
〔実施例〕
つぎに本発明を実施例によシ説明する。
第1図は本発明の一実施例の封止樹脂(2重鎖線の囲み
)を透視した部分平面図である。図において、半導体ペ
レット1の電極パッドとベレット1の周囲に内端部が配
置された多数のリード端子2との間が金属細線3で接続
後、封止樹脂4によル封止されているのであるが、リー
ド端子2は、第2図の平面図に示すような、一方の側辺
が横方向に部分的に凸出した凸出部2aが形成され、さ
らに、凸出部2aの反対側の他方の側辺が部分的に内側
に食い込んだ凹部が形成されたジグザグパターンの平た
い導体金属の原形体から、この原形体の一方の側辺部を
曲げ線としてケ1は垂直に曲けられたところの、第3図
の斜視図に示すよう形をもっている。そして、リード外
端から内端に至る平面径路が、水平面が途中中断して垂
直面に迂回し、また元の水平面に戻る複雑な径路をとっ
ているO 〔発明の効果〕 以上説明したように本発明は、ジグザグな平面パターン
の原形体をL形に曲げることによシ、水平面、垂直面と
移シ変わる径路ができ、かつLの一辺が断続的になるこ
とによシ、外部湿気の浸入がしにくくなる。また外部か
らのストレスにより生じる封止樹脂とリード間のすき間
も、従来のものと比べ起きにくくなる効果が得られる。
【図面の簡単な説明】
第1図は本発明の一実施例の封止樹脂を透視して示した
部分平面図、第2図は第1図のリード端子折曲げ前の平
面図、第3図は、第2図の原形体を折曲げた状態の斜視
図である。 1・・・・・・半導体ペレット、2・・・・・・リード
端子、3・・・・・・金属細線、4・・・・・・封止樹
脂。

Claims (1)

    【特許請求の範囲】
  1. 帯状の金属導体の一方の側辺が横方向に部分的に突出さ
    れ、この突出部の反対側の側辺部が前記突出方向に部分
    的に食い込んだ凹みを有し、かつ、前記突出部が前記一
    方の側辺を曲げ線としてほぼ垂直に曲げられた形のリー
    ド端子を有することを特徴とする半導体装置。
JP61026286A 1986-02-07 1986-02-07 半導体装置 Pending JPS62183546A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61026286A JPS62183546A (ja) 1986-02-07 1986-02-07 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61026286A JPS62183546A (ja) 1986-02-07 1986-02-07 半導体装置

Publications (1)

Publication Number Publication Date
JPS62183546A true JPS62183546A (ja) 1987-08-11

Family

ID=12189052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61026286A Pending JPS62183546A (ja) 1986-02-07 1986-02-07 半導体装置

Country Status (1)

Country Link
JP (1) JPS62183546A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917935A (ja) * 1995-06-29 1997-01-17 Nec Corp リードフレーム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917935A (ja) * 1995-06-29 1997-01-17 Nec Corp リードフレーム

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