JPH0682715B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0682715B2
JPH0682715B2 JP60068282A JP6828285A JPH0682715B2 JP H0682715 B2 JPH0682715 B2 JP H0682715B2 JP 60068282 A JP60068282 A JP 60068282A JP 6828285 A JP6828285 A JP 6828285A JP H0682715 B2 JPH0682715 B2 JP H0682715B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
support plate
semiconductor
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60068282A
Other languages
English (en)
Other versions
JPS61225829A (ja
Inventor
正浩 杉本
邦彦 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60068282A priority Critical patent/JPH0682715B2/ja
Publication of JPS61225829A publication Critical patent/JPS61225829A/ja
Publication of JPH0682715B2 publication Critical patent/JPH0682715B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に係わり、特に大口径半導体ウエ
ハで形成された半導体チップをパッケージングする際
に、半導体チップ材料とパッケージ材料とが膨張係数が
等しく、且つ熱放散の良好なパッケージ構造に関するも
のである。
大口径であるウエハから形成したり、又はウエハそのも
のを用いた半導体チップは、数インチの大きさとなる場
合がある。
この半導体チップには、マイクロコンピータ等の比較的
大規模の回路が形成され、パッケージの配線本数も数千
本に達することになる。
従って、それぞれの配線の接続部の信頼性が必要であ
り、又上記のごとく半導体チップが大きいので、パッケ
ージング後の実際の動作状態で温度が上昇した際に、チ
ップが破損しないような高信頼で安全な構造が要望され
ている。
〔従来の技術〕
第２図は、従来の半導体装置のパッケージ構造を示す主
要断面図である。
大口径半導体チップ１（Full Wafer Size Integration
Chip）があり、この大口径半導体チップはアルミナ材料
で形成された支持板２に収納されていて、大口径半導体
チップと外部配線が行われる支持板２との接続は、アル
ミニウム線又は金線等を使用したボンデングワイヤ３に
よって、それぞれの接続がなされている。
支持板２の上部に取りつけられる封着蓋４は、材料がア
ルミナ又はコバール等で形成されており、支持板２とレ
ジン又は半田付けによって気密封着が行なわれている。
支持板の内部からの外リードピン５はパッケージの壁面
を貫通して、所定部分から外部に引き出されている。
このような大口径の半導体チップでは、ウエハの材料で
あるシリコンの膨張係数が、3.9×10-6であり、一方、
支持板の材料であるアルミナの膨張係数は７×10-6であ
って、両者が大きく異なるために、パッケージが高温に
なると、それぞれの熱膨張の差によって、強度の弱い大
口径の半導体チップが破損することがある他、従来は半
導体チップと支持板との配線が、一本ごとにワイヤボン
デングによって行っていたため、多ピンの場合は長時間
の工数を要し、信頼性も劣るという欠点がある。
〔発明が解決しようとする問題点〕
上記の半導体装置のパッケージの構造では、チップの膨
張係数と、チップを収納するパッケージ材料との膨張係
数の差のためにチップが破損する恐れがあることと、多
数の配線がワイヤボンデングで行われるために多大の時
間を要し、コストアップの原因になる。
〔問題を解決するための手段〕
本発明は、上記問題点を解消した半導体装置を提供する
もので、この課題は、半導体チップがシリコンカーバイ
ドの支持板の収納部に固着され、半導体チップ表面上に
設けられた電極パッドと、該支持板に接着される接続用
セラミック基板に設けられたバンプとが接続されてなる
と共に、該バンプと外部接続端子とは該セラミック基板
を貫通する配線によって結合されていることを特徴とす
る半導体装置よって達成できる。
〔作用〕
本発明は、大口径のウエハ等から形成される半導体チッ
プの材料とパッケージ材料との膨張係数の差によるチッ
プの破損を防止するため、半導体チップへの電気的接続
を短時間に行うために、熱伝導の良好なシリコンと極め
て類似の膨張係数を有するシリコンカーバイドを使用し
て、半導体チップの底部をパッケージに固着し、一方、
配線は半導体チップの表面上に設けられた電極パッドに
よって、上部蓋部の配線とバンプ接続をする。
この蓋部即ち接続用基板は成型焼結されたセラミック板
であり、該基板を貫通して接続線を設けることが容易な
ばかりでなく、外力による変形が殆どないことから、そ
の上面に外部接続用端子を配置することが可能であり、
更にこれを２次元的に配列することも可能である。
従って、半導体チップの破損が防止できると共に、外部
接続用端子数を増して集積回路の高集積化に対応し得る
ようにしたものである。
〔実施例〕
第１図は、本発明の一実施例を示す半導体装置のパッケ
ージングされた状態での主要断面図を示している。
シリコンウエハから形成された半導体チップ11は、シリ
コンの膨張係数と殆ど同様の値を有するシリコンカーバ
イドで形成された支持板12の内部の収納部18に固着さ
れ、半導体チップ11と支持板12は、半田、又はレジンの
ようなソルダ13によって固定されている。
半導体チップには、例えば大きさが４インチ乃至６イン
チのウエハを用い、その周辺部分には配線用の電極パッ
ド14が設けてあり、それに対応する接続用基板15にも外
部配線用の配線16と連結されるバンプ17が設けてあり、
バンプの材料は例えば金等で製作されている。
接続用基板は、シリコンカーバイドにポリイミド等を用
いて形成され、この接続用基板にはシリコンカーバイド
の他に、二酸化シリコンとアルミナの化合物よりなるム
ライト・セラミックスや、ガラスセラミックスを用いる
ことができる。
パッドとバンプの接合は、両者の位置合わせを厳重に行
った後、支持板12と接続用基板15を接合して矢印のよう
に圧着することにより確実に接続されるが、更に支持板
12に接続用基板15を捻子止め又はバネ止めを行ってもよ
い。
この配線用のバンプの数は半導体チップの寸法によっ
て、数千個に達することがあり、高精度に配列されるこ
とが必要である。
このような構造からなる半導体装置は、半導体チップと
パッケージの材料である支持板や接続用基板との膨張係
数の差から発生する半導体ウエハの破損がなく、又接続
用基板と半導体ウエハとのバンプ接続も確実に行われ
て、動作中に発熱するための膨張係数の差による歪力が
なくなり、安定なパッケージ構造が実現できる。
又、アルミナに比較してシリコンカーバイドは熱伝導が
優れており、半導体装置が動作中に発生する熱を放散す
る効果にも大となり、高信頼性のパッケージングを行う
ことができる。
〔発明の効果〕
以上、詳細に説明したように、本発明の半導体装置は、
半導体チップの破損防止と配線の信頼性の向上及び発熱
を低下させる効果があり、高信頼性の半導体装置を供し
得るという効果大なるものがある。
【図面の簡単な説明】
第１図は、本発明の一実施例を示す半導体装置のパッケ
ージの所要断面図、 第２図は、従来の半導体装置のパッケージ構造を示す所
要断面図である。 図において、 11は半導体チップ、12は支持板、 13はソルダ、14は配線用のパッド、 15は接続用基板、16は配線、 17はバンプ、18は収納部、 をそれぞれ示している。

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】半導体チップがシリコンカーバイドの支持
    板の収納部に固着され、半導体チップ表面上に設けられ
    た電極パッドと、該支持板に接着される接続用セラミッ
    ク基板に設けられたバンプとが接続されてなると共に、
    該バンプと外部接続端子とは該セラミック基板を貫通す
    る配線によって結合されていることを特徴とする半導体
    装置。
JP60068282A 1985-03-29 1985-03-29 半導体装置 Expired - Lifetime JPH0682715B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60068282A JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60068282A JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS61225829A JPS61225829A (ja) 1986-10-07
JPH0682715B2 true JPH0682715B2 (ja) 1994-10-19

Family

ID=13369251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60068282A Expired - Lifetime JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Country Status (1)

Country Link
JP (1) JPH0682715B2 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5103290A (en) * 1989-06-16 1992-04-07 General Electric Company Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
JP2015207747A (ja) * 2014-04-17 2015-11-19 政宏 星野 ワイドバンドギャップ半導体デバイス

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4868170A (ja) * 1971-12-20 1973-09-17
JPS5146874A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochino seizohoho
JPS55143042A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS61225829A (ja) 1986-10-07

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