JPH06821Y2 - 半導体装置の実装構造 - Google Patents
半導体装置の実装構造Info
- Publication number
- JPH06821Y2 JPH06821Y2 JP1987195704U JP19570487U JPH06821Y2 JP H06821 Y2 JPH06821 Y2 JP H06821Y2 JP 1987195704 U JP1987195704 U JP 1987195704U JP 19570487 U JP19570487 U JP 19570487U JP H06821 Y2 JPH06821 Y2 JP H06821Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor device
- insulating resin
- protective plate
- protruding electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987195704U JPH06821Y2 (ja) | 1987-12-25 | 1987-12-25 | 半導体装置の実装構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987195704U JPH06821Y2 (ja) | 1987-12-25 | 1987-12-25 | 半導体装置の実装構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01100443U JPH01100443U (US06420036-20020716-C00037.png) | 1989-07-05 |
JPH06821Y2 true JPH06821Y2 (ja) | 1994-01-05 |
Family
ID=31486366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987195704U Expired - Lifetime JPH06821Y2 (ja) | 1987-12-25 | 1987-12-25 | 半導体装置の実装構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06821Y2 (US06420036-20020716-C00037.png) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5589314B2 (ja) * | 2009-06-25 | 2014-09-17 | 株式会社リコー | 電子部品モジュールの製造方法 |
JP6304700B2 (ja) * | 2016-09-26 | 2018-04-04 | 株式会社パウデック | 半導体パッケージ、モジュールおよび電気機器 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5437473B2 (US06420036-20020716-C00037.png) * | 1971-09-09 | 1979-11-15 | ||
JPS61220346A (ja) * | 1985-03-26 | 1986-09-30 | Toshiba Corp | 半導体装置とその製造方法 |
-
1987
- 1987-12-25 JP JP1987195704U patent/JPH06821Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH01100443U (US06420036-20020716-C00037.png) | 1989-07-05 |
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