JPH06342884A - Mos半導体装置及びその製造方法 - Google Patents

Mos半導体装置及びその製造方法

Info

Publication number
JPH06342884A
JPH06342884A JP3263262A JP26326291A JPH06342884A JP H06342884 A JPH06342884 A JP H06342884A JP 3263262 A JP3263262 A JP 3263262A JP 26326291 A JP26326291 A JP 26326291A JP H06342884 A JPH06342884 A JP H06342884A
Authority
JP
Japan
Prior art keywords
mos
transistor
sidewall spacer
gate
impurity region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3263262A
Other languages
English (en)
Japanese (ja)
Inventor
Kyeong-Tae Kim
キム・キョングテ
Do-Chan Choi
チェ・ドチャン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH06342884A publication Critical patent/JPH06342884A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184Manufacturing their gate sidewall spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/859Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90MOSFET type gate sidewall insulating spacer

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP3263262A 1991-07-09 1991-09-13 Mos半導体装置及びその製造方法 Pending JPH06342884A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1991-11609 1991-07-09
KR1019910011609A KR940005802B1 (ko) 1991-07-09 1991-07-09 Cmos 반도체장치 및 그 제조방법

Publications (1)

Publication Number Publication Date
JPH06342884A true JPH06342884A (ja) 1994-12-13

Family

ID=19316971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3263262A Pending JPH06342884A (ja) 1991-07-09 1991-09-13 Mos半導体装置及びその製造方法

Country Status (5)

Country Link
US (1) US5291052A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH06342884A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR940005802B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE4126747A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2257563B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686059B2 (en) 2001-01-31 2004-02-03 Renesas Technology Corp. Semiconductor device manufacturing method and semiconductor device
JP2005191267A (ja) * 2003-12-25 2005-07-14 Fujitsu Ltd Cmos半導体装置の製造方法

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KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
US5786247A (en) * 1994-05-06 1998-07-28 Vlsi Technology, Inc. Low voltage CMOS process with individually adjustable LDD spacers
JP3256084B2 (ja) * 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
US5969388A (en) * 1995-11-21 1999-10-19 Citizen Watch Co., Ltd. Mos device and method of fabricating the same
KR100214468B1 (ko) * 1995-12-29 1999-08-02 구본준 씨모스 소자 제조방법
JP3405631B2 (ja) * 1996-02-28 2003-05-12 互応化学工業株式会社 エポキシ樹脂組成物及びフォトソルダーレジストインク並びにプリント配線板及びその製造方法
JP2924763B2 (ja) * 1996-02-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
US6197627B1 (en) 1996-11-19 2001-03-06 Citizen Watch Co., Ltd. MOS device and method of fabricating the same
JP2982895B2 (ja) * 1997-02-06 1999-11-29 日本電気株式会社 Cmos半導体装置およびその製造方法
JPH10256549A (ja) * 1997-03-14 1998-09-25 Nec Corp 半導体装置及びその製造方法
JP3123465B2 (ja) * 1997-06-09 2001-01-09 日本電気株式会社 Misトランジスタの製造方法
US6221709B1 (en) 1997-06-30 2001-04-24 Stmicroelectronics, Inc. Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor
KR100269510B1 (ko) * 1998-05-20 2000-10-16 윤종용 반도체 장치의 제조 방법
JP2000196071A (ja) * 1998-12-25 2000-07-14 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
JP3530410B2 (ja) * 1999-02-09 2004-05-24 Necエレクトロニクス株式会社 半導体装置の製造方法
JP3530466B2 (ja) * 2000-07-17 2004-05-24 Necエレクトロニクス株式会社 固体撮像装置
US7115462B1 (en) 2001-11-28 2006-10-03 Cypress Semiconductor Corp. Processes providing high and low threshold p-type and n-type transistors
US6882013B2 (en) * 2002-01-31 2005-04-19 Texas Instruments Incorporated Transistor with reduced short channel effects and method
US7416927B2 (en) * 2002-03-26 2008-08-26 Infineon Technologies Ag Method for producing an SOI field effect transistor
DE10221884A1 (de) * 2002-05-16 2003-11-27 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung, Schicht-Anordnung und Speicher-Anordnung
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
US6806584B2 (en) * 2002-10-21 2004-10-19 International Business Machines Corporation Semiconductor device structure including multiple fets having different spacer widths
US6864135B2 (en) * 2002-10-31 2005-03-08 Freescale Semiconductor, Inc. Semiconductor fabrication process using transistor spacers of differing widths
DE10300687A1 (de) 2003-01-10 2004-07-22 Infineon Technologies Ag Integrierte Halbleiterschaltung insbesondere Halbleiterspeicherschaltung und Herstellungsverfahren dafür
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US6905923B1 (en) * 2003-07-15 2005-06-14 Advanced Micro Devices, Inc. Offset spacer process for forming N-type transistors
US7033879B2 (en) * 2004-04-29 2006-04-25 Texas Instruments Incorporated Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
US7223647B2 (en) * 2004-11-05 2007-05-29 Taiwan Semiconductor Manufacturing Company Method for forming integrated advanced semiconductor device using sacrificial stress layer
KR100585180B1 (ko) * 2005-02-21 2006-05-30 삼성전자주식회사 동작 전류가 개선된 반도체 메모리 소자 및 그 제조방법
JP4460552B2 (ja) * 2006-07-04 2010-05-12 シャープ株式会社 半導体記憶装置
CN105633154B (zh) * 2014-11-26 2020-04-21 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
KR102394938B1 (ko) 2015-05-21 2022-05-09 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법
JP2019029448A (ja) * 2017-07-27 2019-02-21 キヤノン株式会社 撮像装置、カメラおよび撮像装置の製造方法
CN109494191A (zh) * 2018-11-19 2019-03-19 武汉新芯集成电路制造有限公司 半导体器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
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JPS6484659A (en) * 1987-09-28 1989-03-29 Toshiba Corp Manufacture of semiconductor device
JPH01283956A (ja) * 1988-05-11 1989-11-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

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DE244607C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) *
DE401113C (de) * 1923-04-22 1924-08-26 Fritz Schuster Heizbare Form zum Appretieren von Kleidungsstuecken
US4295897B1 (en) * 1979-10-03 1997-09-09 Texas Instruments Inc Method of making cmos integrated circuit device
US4474624A (en) * 1982-07-12 1984-10-02 Intel Corporation Process for forming self-aligned complementary source/drain regions for MOS transistors
US4470852A (en) * 1982-09-03 1984-09-11 Ncr Corporation Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions
US4577391A (en) * 1984-07-27 1986-03-25 Monolithic Memories, Inc. Method of manufacturing CMOS devices
JPS61105862A (ja) * 1984-10-30 1986-05-23 Toshiba Corp 半導体装置
US4760033A (en) * 1986-04-08 1988-07-26 Siemens Aktiengesellschaft Method for the manufacture of complementary MOS field effect transistors in VLSI technology
JP2559397B2 (ja) * 1987-03-16 1996-12-04 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5024960A (en) * 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
JPH0821687B2 (ja) * 1989-05-31 1996-03-04 富士通株式会社 半導体装置及びその製造方法
US5021354A (en) * 1989-12-04 1991-06-04 Motorola, Inc. Process for manufacturing a semiconductor device
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6484659A (en) * 1987-09-28 1989-03-29 Toshiba Corp Manufacture of semiconductor device
JPH01283956A (ja) * 1988-05-11 1989-11-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686059B2 (en) 2001-01-31 2004-02-03 Renesas Technology Corp. Semiconductor device manufacturing method and semiconductor device
JP2005191267A (ja) * 2003-12-25 2005-07-14 Fujitsu Ltd Cmos半導体装置の製造方法

Also Published As

Publication number Publication date
GB2257563A (en) 1993-01-13
KR940005802B1 (ko) 1994-06-23
GB9117254D0 (en) 1991-09-25
US5291052A (en) 1994-03-01
DE4126747C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-05-06
DE4126747A1 (de) 1993-01-21
GB2257563B (en) 1995-06-28

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