JPH06195475A - マイクロコントローラｉ／ｏポート割込機構 - Google Patents

マイクロコントローラｉ／ｏポート割込機構

Info

Publication number
JPH06195475A
JPH06195475A JP5170220A JP17022093A JPH06195475A JP H06195475 A JPH06195475 A JP H06195475A JP 5170220 A JP5170220 A JP 5170220A JP 17022093 A JP17022093 A JP 17022093A JP H06195475 A JPH06195475 A JP H06195475A
Authority
JP
Japan
Prior art keywords
interrupt
port
register
microcontroller
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5170220A
Other languages
English (en)
Japanese (ja)
Inventor
Dale E Gulick
デイル・イー・グリック
Joseph William Peterson
ジョセフ・ウィリアム・ピーターソン
Munehiro Yoshikawa
宗宏 吉川
Hiroshi Matsubara
弘 松原
Toshihiro Fujita
敏弘 藤田
Kazue Tsurumi
和重 鶴身
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JPH06195475A publication Critical patent/JPH06195475A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
JP5170220A 1992-07-21 1993-07-09 マイクロコントローラｉ／ｏポート割込機構 Withdrawn JPH06195475A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US917497 1992-07-21
US07/917,497 US5448743A (en) 1992-07-21 1992-07-21 General I/O port interrupt mechanism

Publications (1)

Publication Number Publication Date
JPH06195475A true JPH06195475A (ja) 1994-07-15

Family

ID=25438878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5170220A Withdrawn JPH06195475A (ja) 1992-07-21 1993-07-09 マイクロコントローラｉ／ｏポート割込機構

Country Status (6)

Country Link
US (1) US5448743A (zh)
EP (1) EP0581480B1 (zh)
JP (1) JPH06195475A (zh)
KR (1) KR940002710A (zh)
CN (1) CN1069425C (zh)
DE (1) DE69325321T2 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002877A (en) * 1994-03-23 1999-12-14 Fujitsu Limited Interrupt control method for controlling an interrupt from a peripheral device to a processor
US6421754B1 (en) * 1994-12-22 2002-07-16 Texas Instruments Incorporated System management mode circuits, systems and methods
US5768599A (en) * 1995-02-28 1998-06-16 Nec Corporation Interrupt managing system for real-time operating system
GB9509626D0 (en) * 1995-05-12 1995-07-05 Sgs Thomson Microelectronics Processor interrupt control
US5640570A (en) * 1996-01-26 1997-06-17 International Business Machines Corporation Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer
US5787290A (en) * 1996-12-20 1998-07-28 International Business Machines Corporation Adapter with an onboard interrupt controller for controlling a computer system
US5819095A (en) * 1996-12-20 1998-10-06 International Business Machines Corporation Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
US5905913A (en) * 1997-04-24 1999-05-18 International Business Machines Corporation System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor
US6032204A (en) * 1998-03-09 2000-02-29 Advanced Micro Devices, Inc. Microcontroller with a synchronous serial interface and a two-channel DMA unit configured together for providing DMA requests to the first and second DMA channel
US6212593B1 (en) * 1998-06-01 2001-04-03 Advanced Micro Devices, Inc. Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system
US6606677B1 (en) 2000-03-07 2003-08-12 International Business Machines Corporation High speed interrupt controller
US6857036B2 (en) * 2001-07-17 2005-02-15 Hewlett Packard Development Company, L.P. Hardware method for implementing atomic semaphore operations using code macros
JP2004199187A (ja) * 2002-12-16 2004-07-15 Matsushita Electric Ind Co Ltd Ｃｐｕ内蔵ｌｓｉ
US7584316B2 (en) * 2003-10-14 2009-09-01 Broadcom Corporation Packet manager interrupt mapper
GB2409543B (en) * 2003-12-23 2006-11-01 Advanced Risc Mach Ltd Interrupt masking control
US9753765B1 (en) * 2004-03-22 2017-09-05 Altera Corporation Multi-processor integrated circuits
JP2005309652A (ja) * 2004-04-20 2005-11-04 Fujitsu Ltd マイクロコントローラ
US9367321B2 (en) * 2007-03-14 2016-06-14 Xmos Limited Processor instruction set for controlling an event source to generate events used to schedule threads
CN101645051B (zh) * 2009-06-10 2013-04-24 无锡中星微电子有限公司 一种gpio中断控制装置、芯片及一种gpio中断控制方法
US10198062B2 (en) 2009-11-20 2019-02-05 Nxp B.V. Microprocessor to resume clocking and execution based on external input pattern detection
WO2014138472A2 (en) * 2013-03-06 2014-09-12 Robotex Inc. System and method for collecting and processing data and for utilizing robotic and/or human resources
CN104111866A (zh) * 2013-04-18 2014-10-22 鸿富锦精密工业（深圳）有限公司 中断控制系统和方法
US11962306B2 (en) * 2021-06-29 2024-04-16 Nvidia Corporation Clock anomaly detection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825902A (en) * 1973-04-30 1974-07-23 Ibm Interlevel communication in multilevel priority interrupt system
US4159516A (en) * 1976-03-23 1979-06-26 Texas Instruments Incorporated Input/output controller having selectable timing and maskable interrupt generation
US4631670A (en) * 1984-07-11 1986-12-23 Ibm Corporation Interrupt level sharing
US5142625A (en) * 1985-06-12 1992-08-25 Minolta Camera Kabushiki Kaisha One-chip microcomputer including a programmable logic array for interrupt control
JPS61285545A (ja) * 1985-06-12 1986-12-16 Minolta Camera Co Ltd ワンチツプマイクロコンピユ−タ
US4779195A (en) * 1985-06-28 1988-10-18 Hewlett-Packard Company Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
DE3856067T2 (de) * 1987-07-06 1998-06-10 Hitachi Ltd Datenprozessor mit einer Unterbrechungsfunktion
CA1319441C (en) * 1988-09-09 1993-06-22 Paul R. Culley Programmable interrupt controller

Also Published As

Publication number Publication date
KR940002710A (ko) 1994-02-19
DE69325321T2 (de) 2000-03-23
EP0581480A1 (en) 1994-02-02
CN1069425C (zh) 2001-08-08
DE69325321D1 (de) 1999-07-22
EP0581480B1 (en) 1999-06-16
CN1082736A (zh) 1994-02-23
US5448743A (en) 1995-09-05

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Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20001003