JPH0587856B2 - - Google Patents

Info

Publication number
JPH0587856B2
JPH0587856B2 JP58047481A JP4748183A JPH0587856B2 JP H0587856 B2 JPH0587856 B2 JP H0587856B2 JP 58047481 A JP58047481 A JP 58047481A JP 4748183 A JP4748183 A JP 4748183A JP H0587856 B2 JPH0587856 B2 JP H0587856B2
Authority
JP
Japan
Prior art keywords
processor
mode
input
program
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58047481A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59172059A (ja
Inventor
Shinji Nishibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP4748183A priority Critical patent/JPS59172059A/ja
Publication of JPS59172059A publication Critical patent/JPS59172059A/ja
Publication of JPH0587856B2 publication Critical patent/JPH0587856B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP4748183A 1983-03-22 1983-03-22 電子計算機システム Granted JPS59172059A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4748183A JPS59172059A (ja) 1983-03-22 1983-03-22 電子計算機システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4748183A JPS59172059A (ja) 1983-03-22 1983-03-22 電子計算機システム

Publications (2)

Publication Number Publication Date
JPS59172059A JPS59172059A (ja) 1984-09-28
JPH0587856B2 true JPH0587856B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-12-20

Family

ID=12776317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4748183A Granted JPS59172059A (ja) 1983-03-22 1983-03-22 電子計算機システム

Country Status (1)

Country Link
JP (1) JPS59172059A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2695773B2 (ja) * 1986-09-25 1998-01-14 株式会社東芝 マルチｃｐｕ制御方式
GB0417069D0 (en) * 2004-07-30 2004-09-01 Hewlett Packard Development Co Methods, apparatus and software for validating entries made on a form
EP1832977A3 (en) * 2006-03-09 2007-10-10 Telefonaktiebolaget LM Ericsson (publ) Platform boot with bridge support

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605029B2 (ja) * 1979-06-08 1985-02-07 三菱電機株式会社 多重計算機システムにおける運転管理装置
JPS5717058A (en) * 1980-07-05 1982-01-28 Nec Corp Control system of microprogram
JPS5719830A (en) * 1980-07-11 1982-02-02 Hitachi Ltd Multiple connection system

Also Published As

Publication number Publication date
JPS59172059A (ja) 1984-09-28

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