JPH0586690B2 - - Google Patents

Info

Publication number
JPH0586690B2
JPH0586690B2 JP60113471A JP11347185A JPH0586690B2 JP H0586690 B2 JPH0586690 B2 JP H0586690B2 JP 60113471 A JP60113471 A JP 60113471A JP 11347185 A JP11347185 A JP 11347185A JP H0586690 B2 JPH0586690 B2 JP H0586690B2
Authority
JP
Japan
Prior art keywords
clock
circuit
transmission
generated
sending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60113471A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61270937A (ja
Inventor
Kazuo Kishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60113471A priority Critical patent/JPS61270937A/ja
Publication of JPS61270937A publication Critical patent/JPS61270937A/ja
Publication of JPH0586690B2 publication Critical patent/JPH0586690B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP60113471A 1985-05-27 1985-05-27 N対nル−プ伝送におけるビツト同期装置 Granted JPS61270937A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60113471A JPS61270937A (ja) 1985-05-27 1985-05-27 N対nル−プ伝送におけるビツト同期装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60113471A JPS61270937A (ja) 1985-05-27 1985-05-27 N対nル−プ伝送におけるビツト同期装置

Publications (2)

Publication Number Publication Date
JPS61270937A JPS61270937A (ja) 1986-12-01
JPH0586690B2 true JPH0586690B2 (enrdf_load_stackoverflow) 1993-12-14

Family

ID=14613092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60113471A Granted JPS61270937A (ja) 1985-05-27 1985-05-27 N対nル−プ伝送におけるビツト同期装置

Country Status (1)

Country Link
JP (1) JPS61270937A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS61270937A (ja) 1986-12-01

Similar Documents

Publication Publication Date Title
US5467464A (en) Adaptive clock skew and duty cycle compensation for a serial data bus
US4661965A (en) Timing recovery circuit for manchester coded data
JP3067832B2 (ja) 信号位相装置
JPH0586690B2 (enrdf_load_stackoverflow)
US6023768A (en) Phase locked distributed time reference for digital processing and method therefor
JPH0320177B2 (enrdf_load_stackoverflow)
EP0602898A1 (en) Method and apparatus for synchronizing transmission of modem
JPH04352535A (ja) ループ式伝送路制御方式
JPH0653955A (ja) パラレルビット同期方式
JPS6350896B2 (enrdf_load_stackoverflow)
JP3427761B2 (ja) 同期回路
JP3026391B2 (ja) ビット列補償回路
JPH05244134A (ja) データ同期回路
JPH0530068A (ja) 調歩式データ多重化方式
JPH05130112A (ja) データ伝送方式
JPS6172443A (ja) デイジタル多重化伝送システムの同期方式
JPH0583224A (ja) スタツフ多重化装置
JPH05114897A (ja) 位相同期回路
JPH0542210B2 (enrdf_load_stackoverflow)
JPH037172B2 (enrdf_load_stackoverflow)
JPH09270783A (ja) フレーム同期装置
JPS60235557A (ja) ル−プ式伝送路間接続方式
JPH08340312A (ja) フレーム同期制御回路
JPS60194850A (ja) 位相同期送受信装置
JPH07114400B2 (ja) フレーム同期方式