JPH0586659B2 - - Google Patents

Info

Publication number
JPH0586659B2
JPH0586659B2 JP57187387A JP18738782A JPH0586659B2 JP H0586659 B2 JPH0586659 B2 JP H0586659B2 JP 57187387 A JP57187387 A JP 57187387A JP 18738782 A JP18738782 A JP 18738782A JP H0586659 B2 JPH0586659 B2 JP H0586659B2
Authority
JP
Japan
Prior art keywords
film
substrate
etching
sio
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57187387A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5978542A (ja
Inventor
Kohei Ebara
Susumu Muramoto
Seitaro Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57187387A priority Critical patent/JPS5978542A/ja
Publication of JPS5978542A publication Critical patent/JPS5978542A/ja
Publication of JPH0586659B2 publication Critical patent/JPH0586659B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP57187387A 1982-10-27 1982-10-27 半導体装置の製造方法 Granted JPS5978542A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57187387A JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57187387A JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5978542A JPS5978542A (ja) 1984-05-07
JPH0586659B2 true JPH0586659B2 (cg-RX-API-DMAC7.html) 1993-12-13

Family

ID=16205124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57187387A Granted JPS5978542A (ja) 1982-10-27 1982-10-27 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5978542A (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2811689B2 (ja) * 1988-07-05 1998-10-15 松下電器産業株式会社 半導体装置の製造方法
KR100763538B1 (ko) * 2006-08-29 2007-10-05 삼성전자주식회사 마스크 패턴의 형성 방법 및 이를 이용한 미세 패턴의 형성방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669833A (en) * 1979-11-09 1981-06-11 Toshiba Corp Fine processing method of thin film
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
JPS56131945A (en) * 1980-03-19 1981-10-15 Matsushita Electric Ind Co Ltd Forming method of silicon oxidation film
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
JPS5919349A (ja) * 1982-07-26 1984-01-31 Toshiba Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPS5978542A (ja) 1984-05-07

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