JPH0573272B2 - - Google Patents

Info

Publication number
JPH0573272B2
JPH0573272B2 JP62012681A JP1268187A JPH0573272B2 JP H0573272 B2 JPH0573272 B2 JP H0573272B2 JP 62012681 A JP62012681 A JP 62012681A JP 1268187 A JP1268187 A JP 1268187A JP H0573272 B2 JPH0573272 B2 JP H0573272B2
Authority
JP
Japan
Prior art keywords
output
power
circuits
pad
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62012681A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63179560A (ja
Inventor
Makoto Myazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62012681A priority Critical patent/JPS63179560A/ja
Publication of JPS63179560A publication Critical patent/JPS63179560A/ja
Publication of JPH0573272B2 publication Critical patent/JPH0573272B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP62012681A 1987-01-21 1987-01-21 集積回路記憶装置 Granted JPS63179560A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62012681A JPS63179560A (ja) 1987-01-21 1987-01-21 集積回路記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62012681A JPS63179560A (ja) 1987-01-21 1987-01-21 集積回路記憶装置

Publications (2)

Publication Number Publication Date
JPS63179560A JPS63179560A (ja) 1988-07-23
JPH0573272B2 true JPH0573272B2 (enExample) 1993-10-14

Family

ID=11812121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62012681A Granted JPS63179560A (ja) 1987-01-21 1987-01-21 集積回路記憶装置

Country Status (1)

Country Link
JP (1) JPS63179560A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01139437U (enExample) * 1988-03-18 1989-09-22

Also Published As

Publication number Publication date
JPS63179560A (ja) 1988-07-23

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