JPH0542028B2 - - Google Patents

Info

Publication number
JPH0542028B2
JPH0542028B2 JP62231999A JP23199987A JPH0542028B2 JP H0542028 B2 JPH0542028 B2 JP H0542028B2 JP 62231999 A JP62231999 A JP 62231999A JP 23199987 A JP23199987 A JP 23199987A JP H0542028 B2 JPH0542028 B2 JP H0542028B2
Authority
JP
Japan
Prior art keywords
output
input
storage element
semaphore
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62231999A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6389961A (ja
Inventor
Jei Miraa Maikuru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics America Inc
Original Assignee
Integrated Device Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Device Technology Inc filed Critical Integrated Device Technology Inc
Publication of JPS6389961A publication Critical patent/JPS6389961A/ja
Publication of JPH0542028B2 publication Critical patent/JPH0542028B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
JP62231999A 1986-09-17 1987-09-16 セマフォ回路 Granted JPS6389961A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/908,302 US4780822A (en) 1986-09-17 1986-09-17 Semaphore circuit for shared memory cells
US908302 1986-09-17

Publications (2)

Publication Number Publication Date
JPS6389961A JPS6389961A (ja) 1988-04-20
JPH0542028B2 true JPH0542028B2 (fr) 1993-06-25

Family

ID=25425556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231999A Granted JPS6389961A (ja) 1986-09-17 1987-09-16 セマフォ回路

Country Status (4)

Country Link
US (1) US4780822A (fr)
EP (1) EP0261497B1 (fr)
JP (1) JPS6389961A (fr)
DE (1) DE3786973T2 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2749819B2 (ja) * 1987-10-26 1998-05-13 松下電工株式会社 共有メモリ制御方式
US4928222A (en) * 1988-10-31 1990-05-22 International Business Machines Corporation Enhanced semaphore architecture
US5669002A (en) * 1990-06-28 1997-09-16 Digital Equipment Corp. Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory
US5196906A (en) * 1990-06-29 1993-03-23 Tma Technologies, Inc. Modular scatterometer with interchangeable scanning heads
US5261106A (en) * 1991-12-13 1993-11-09 S-Mos Systems, Inc. Semaphore bypass
US5448714A (en) * 1992-01-02 1995-09-05 Integrated Device Technology, Inc. Sequential-access and random-access dual-port memory buffer
WO1993024888A1 (fr) * 1992-05-22 1993-12-09 Massachusetts Institute Of Technology Resolveur de reponse pour memoires associatives et processeurs paralleles
US5440746A (en) * 1992-11-06 1995-08-08 Seiko Epson Corporation System and method for synchronizing processors in a parallel processing environment
US5931923A (en) * 1996-02-16 1999-08-03 Advanced Micro Devices, Inc. System for accessing control to a peripheral device utilizing a synchronization primitive within the peripheral device
US5869979A (en) 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
KR100302924B1 (ko) * 1996-12-20 2001-09-22 포만 제프리 엘 데이터통신장치
US6212607B1 (en) 1997-01-17 2001-04-03 Integrated Device Technology, Inc. Multi-ported memory architecture using single-ported RAM
US6108756A (en) * 1997-01-17 2000-08-22 Integrated Device Technology, Inc. Semaphore enhancement to allow bank selection of a shared resource memory device
FR2759472B1 (fr) * 1997-02-12 1999-05-07 Thomson Csf Registre semaphore rapide a fonctionnement securise sans protocole de bus specifique
US6892258B1 (en) * 2001-10-26 2005-05-10 Lsi Logic Corporation Hardware semaphores for a multi-processor system within a shared memory architecture
US9292533B2 (en) 2010-06-08 2016-03-22 Dell Products L.P. Systems and methods for improving storage efficiency in an information handling system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150054A (en) * 1979-05-11 1980-11-21 Nissin Electric Co Ltd Multi-computer system
JPS6194170A (ja) * 1984-10-15 1986-05-13 Oki Electric Ind Co Ltd 同期形ア−ビタ回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50113316U (fr) * 1974-02-25 1975-09-16
JPS5837585B2 (ja) * 1975-09-30 1983-08-17 株式会社東芝 ケイサンキソウチ
JPS52130246A (en) * 1976-04-24 1977-11-01 Fujitsu Ltd Memory access control system
JPS547252A (en) * 1977-06-20 1979-01-19 Hitachi Ltd Program control system
US4380798A (en) * 1980-09-15 1983-04-19 Motorola, Inc. Semaphore register including ownership bits
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
US4594657A (en) * 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150054A (en) * 1979-05-11 1980-11-21 Nissin Electric Co Ltd Multi-computer system
JPS6194170A (ja) * 1984-10-15 1986-05-13 Oki Electric Ind Co Ltd 同期形ア−ビタ回路

Also Published As

Publication number Publication date
DE3786973D1 (de) 1993-09-16
US4780822A (en) 1988-10-25
JPS6389961A (ja) 1988-04-20
EP0261497B1 (fr) 1993-08-11
EP0261497A2 (fr) 1988-03-30
EP0261497A3 (en) 1989-09-20
DE3786973T2 (de) 1994-03-10

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