JPH0483367A - 電力用半導体装置 - Google Patents

電力用半導体装置

Info

Publication number
JPH0483367A
JPH0483367A JP2196330A JP19633090A JPH0483367A JP H0483367 A JPH0483367 A JP H0483367A JP 2196330 A JP2196330 A JP 2196330A JP 19633090 A JP19633090 A JP 19633090A JP H0483367 A JPH0483367 A JP H0483367A
Authority
JP
Japan
Prior art keywords
fixed
plate
metal base
insulating substrate
ceramic insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2196330A
Other languages
English (en)
Other versions
JP2504610B2 (ja
Inventor
Junichi Nakao
中尾 淳一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2196330A priority Critical patent/JP2504610B2/ja
Priority to DE69123298T priority patent/DE69123298T2/de
Priority to EP91112419A priority patent/EP0468475B1/en
Priority to KR1019910012787A priority patent/KR950000203B1/ko
Priority to US07/736,230 priority patent/US5216279A/en
Publication of JPH0483367A publication Critical patent/JPH0483367A/ja
Application granted granted Critical
Publication of JP2504610B2 publication Critical patent/JP2504610B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 、[発明の目的] (産業上の利用分野) この発明は特にモータコントロール等に使用される、ペ
レットサイズの大きい電力用半導体装置に関する。
(従来の技術) 第4図は従来の放熱金属ベースより電極を取り出すタイ
プの電力用半導体装置の構成図である。
放熱金属ベース21上に半導体ペレット22をマウント
する際、金属とシリコンの熱膨張差によるペレットのク
ラック防止対策として放熱金属ベース21とペレット2
2との間には金属板、例えばモリブデン板23が挿入さ
れており、放熱金属ベース21、モリブデン板23及び
ペレット22の相互間は例えば、はんだ24により固着
されている。また、電極取出し部は、放熱金属ベース2
1上にメタライズセラミック26及びCu(銅)からな
る電極27が順次はんだ24によりマウントされている
。ペレット22と電極27とはアルミニウムワイヤ28
により配線されている。
しかしなから、このような構成では、製造工程上、はん
だ付は工程数と共に部品点数が多くなるので、マウント
、ボンディング工程の自動化が困難であり、手作業によ
る組み立てラインを構成するのが現状である。
(発明が解決しようとする課題) このように、従来では製造工程上、はんだ付は工程数と
共に部品点数が多くなってしまい、マウント、ボンディ
ング工程の自動化が困難であり、手作業による組み立て
ラインにより製造コストが高いという欠点があった。
この発明は上記のような事情を考慮してなされたもので
あり、その目的は、部品点数を削減すると共に製造工程
数を削減し、組み立てラインの自動化を図ることができ
る電力用半導体装置を提供することにある。
[発明の構成] (課題を解決するための手段) この発明の電力用半導体装置は、セラミック系絶縁基板
と、前記セラミック系絶縁基板の表面から一側面を介し
裏面に連続して巻き付くように固着された第1の導電板
と、前記第1の導電板の両側の前記セラミック系絶縁基
板の表面にそれぞれ固着された第2の導電板と、前記セ
ラミック系絶縁基板の表面における第1の導電板上に固
着された半導体ペレットと、前記半導体ペレットの電極
パッドと前記第2の導電板とを配線するボンディング用
のワイヤと、前記前記半導体ペレットが固着されていな
いセラミック系絶縁基板の裏面における第1の導電板と
固着される放熱金属ベースとから構成される。
(作 用) この発明では、半導体ペレットが固着される導電板がセ
ラミック系絶縁基板の表面から一側面を介して裏面に連
続的に存在する構成を用いることにより、製造工程数が
大幅に削減する。また、後に固着される放熱金属ベース
と半導体ペレットとの電気的接続を付属部品なしに実現
する。
(実施例) 以下、図面を参照してこの発明を実施例により説明する
まず、この発明の目的における製造工程における部品点
数の削減については、D B C(DirectBon
d Copper)基板と呼ばれる、セラミック板とC
u板を直接張り付けた基板を用いることで、大略達成さ
れる。
第3図はこの発明の前提となるDBC基板を放熱金属ベ
ースの上に固定した斜視図である。放熱金属ベース11
は、例えばCu板にニッケルメッキしたものやアルミニ
ウム板が使われる。この放熱金属ベースll上にDBC
基板12が固定されている。
DEC基板12は、セラミック板18表面上に半導体ペ
レットが固着されるCu板14、半導体ペレットの電極
となるCu板15が固定されているものである。セラミ
ック板13とCu板14.15とは例えば高温の酸化性
雰囲気中で固着される。図示しないが、セラミック板1
3の裏面にもCu板が固着されている。
このDBC基板12が放熱金属ベース11上にはんだ等
で固着される。ここで、半導体ペレットが固着されるC
u板14と放熱金属ベース11とは電気的に接続される
必要がある。この場合、Cu板14と放熱金属ベース1
1とは、その間に絶縁体のセラミック板13を介在させ
ており、このままでは半導体ペレットと放熱金属ベース
11とは電気的に接続されない。そこで、ターミナル金
属1Bによるはんだ付けで、半導体ペレットが搭載され
るCu板14は放熱金属ベース11と電気的に接続され
る構造をとっている。
しかし、このターミナル金属IBの取付けが自動化を困
難にさせる原因にもなっており、量産性の向上を妨げて
いる。
そこで、この発明では上記ターミナル金属1Bの取付け
が不要になるようなりBC基板を構成する。
第1図(a)、(b)はそれぞれこの発明の一実施例に
係るDBC基板の構成を示す斜視図であり、(a)は半
導体ペレットが固着される面(表面)、(b)は放熱金
属ベースが固着される面(裏面)を示している。そして
、第1図(C)は同図(a)もしくは(b)のA−A’
線に沿った断面図である。
半導体ペレットが固着されるCu板1が、セラミック板
2の表面から一つの側面を介して裏面に巻き付くように
固着されている。セラミック板lの半導体ペレットが固
着される表面上において、このCu板1の両側は半導体
ペレットの電極となるCu板3が固着されている。セラ
ミック板2とCu板1.3とは例えば高温の酸化性雰囲
気中で固着される。このようにしてDEC基板4が構成
される。
上記実施例の構成によれば、第1図(c)のごとく、C
u板lのU字形の溝にセラミック板2を差し込むことが
できるので、構造が簡単なうえ固定し易く、裏面への熱
伝導性も良くなるという利点が得られる。
第2図は上記DEC基板4を用いて電力用半導体装置の
組み立てを実施した場合の構成図である。
DEC基板4におけるCu板1に半導体ペレット5がは
んだ6等によりマウントされている。ペレット5とCu
板3 (電極)とはアルミニウムワイヤ7により配線さ
れている。
このようなりEC基板4が放熱金属ベース8上に固着さ
れる。この場合、Cu板1は絶縁体のセラミック板2の
表面から裏面にかけて連続的に存在するので、放熱金属
ベース8とDBCEC基板4はんだ6等による通常の接
着のみで半導体ペレット5と放熱金属ベース8とが電気
的に接続される。
従って、上記第3図に示すようなターミナル金属16は
不要になる。
上記実施例によれば、組み立て工程が簡素化され、組み
立てラインの自動化が可能となり、製品コストの削減を
図ることができる。
[発明の効果] 以上説明したようにこの発明によれば、半導体ペレット
が固着されるCu板かDBC基板の表面から裏面にかけ
て連続的に存在する構成を用いることにより、部品点数
を削減すると共に製造工程数を削減し、組み立てライン
の自動化を図ることができる電力用半導体装置が提供で
きる。
【図面の簡単な説明】
第1図(a)、(b)はそれぞれこの発明の一実施例に
係るDEC基板の構成を示す斜視図、第1図(c)は同
図(a)または(b)のA−A′線に沿った断面図、 第2図は上記第1図(a、)〜(c)で示すDBC基板
を用いて電力用半導体装置の組み立てを実施した場合の
構成図、 第3図はこの発明の前提となるDEC基板を放熱金属ベ
ースの上に固定した斜視図、 第4図は従来の放熱金属ベースより電極を取り出すタイ
プの電力用半導体装置の構成図である。 ■、3・・・Cu板、 2・・・セラミック板、4・・
・DEC基板、5・・・半導体ペレット、6・・・はん
だ、7・・・アルミニウムワイヤ、8・・・放熱金属ベ
ース。 出願人代理人 弁理士 鈴江武彦 第1図

Claims (1)

  1. 【特許請求の範囲】 セラミック系絶縁基板と、 前記セラミック系絶縁基板の表面から一側面を介し裏面
    に連続して巻き付くように固着された第1の導電板と、 前記第1の導電板の両側の前記セラミック系絶縁基板の
    表面にそれぞれ固着された第2の導電板と、 前記セラミック系絶縁基板の表面における第1の導電板
    上に固着された半導体ペレットと、前記半導体ペレット
    の電極パッドと前記第2の導電板とを配線するボンディ
    ング用のワイヤと、前記半導体ペレットが固着されてい
    ないセラミック系絶縁基板の裏面における第1の導電板
    と固着される放熱金属ベースと を具備したことを特徴とする電力用半導体装置。
JP2196330A 1990-07-26 1990-07-26 電力用半導体装置 Expired - Lifetime JP2504610B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2196330A JP2504610B2 (ja) 1990-07-26 1990-07-26 電力用半導体装置
DE69123298T DE69123298T2 (de) 1990-07-26 1991-07-24 Leistungshalbleiteranordnung, geeignet zur Automation der Herstellung
EP91112419A EP0468475B1 (en) 1990-07-26 1991-07-24 Power semiconductor device suitable for automation of production
KR1019910012787A KR950000203B1 (ko) 1990-07-26 1991-07-25 전력용 반도체 장치
US07/736,230 US5216279A (en) 1990-07-26 1991-07-26 Power semiconductor device suitable for automation of production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2196330A JP2504610B2 (ja) 1990-07-26 1990-07-26 電力用半導体装置

Publications (2)

Publication Number Publication Date
JPH0483367A true JPH0483367A (ja) 1992-03-17
JP2504610B2 JP2504610B2 (ja) 1996-06-05

Family

ID=16356033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2196330A Expired - Lifetime JP2504610B2 (ja) 1990-07-26 1990-07-26 電力用半導体装置

Country Status (5)

Country Link
US (1) US5216279A (ja)
EP (1) EP0468475B1 (ja)
JP (1) JP2504610B2 (ja)
KR (1) KR950000203B1 (ja)
DE (1) DE69123298T2 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US5808358A (en) * 1994-11-10 1998-09-15 Vlt Corporation Packaging electrical circuits
US5876859A (en) * 1994-11-10 1999-03-02 Vlt Corporation Direct metal bonding
US5945130A (en) * 1994-11-15 1999-08-31 Vlt Corporation Apparatus for circuit encapsulation
US8587105B2 (en) 2011-09-21 2013-11-19 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616421A (en) * 1991-04-08 1997-04-01 Aluminum Company Of America Metal matrix composites containing electrical insulators
US5444300A (en) * 1991-08-09 1995-08-22 Sharp Kabushiki Kaisha Semiconductor apparatus with heat sink
US5309014A (en) * 1992-04-02 1994-05-03 Motorola Inc. Transistor package
DE4300516C2 (de) * 1993-01-12 2001-05-17 Ixys Semiconductor Gmbh Leistungshalbleitermodul
US5395679A (en) * 1993-03-29 1995-03-07 Delco Electronics Corp. Ultra-thick thick films for thermal management and current carrying capabilities in hybrid circuits
US5480727A (en) * 1994-02-03 1996-01-02 Motorola, Inc. Electronic device assembly and method for making
US5565705A (en) * 1994-05-02 1996-10-15 Motorola, Inc. Electronic module for removing heat from a semiconductor die
US5956231A (en) * 1994-10-07 1999-09-21 Hitachi, Ltd. Semiconductor device having power semiconductor elements
DE69603664T2 (de) * 1995-05-30 2000-03-16 Motorola Inc Hybrid-Multichip-Modul und Verfahren zur seiner Herstellung
US5798566A (en) * 1996-01-11 1998-08-25 Ngk Spark Plug Co., Ltd. Ceramic IC package base and ceramic cover
EP0805492B1 (de) * 1996-04-03 2004-06-30 Jürgen Dr.-Ing. Schulz-Harder Gewölbtes Metall-Keramik-Substrat
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board
US6777784B1 (en) * 2000-10-17 2004-08-17 National Semiconductor Corporation Bipolar transistor-based electrostatic discharge (ESD) protection structure with a heat sink
US7443229B1 (en) 2001-04-24 2008-10-28 Picor Corporation Active filtering
US6985341B2 (en) * 2001-04-24 2006-01-10 Vlt, Inc. Components having actively controlled circuit elements
JP4806803B2 (ja) * 2003-10-21 2011-11-02 Dowaメタルテック株式会社 金属−セラミックス接合基板およびその製造方法
EP2302688A1 (de) 2009-09-23 2011-03-30 Robert Bosch GmbH Verfahren zur Herstellung eines Substrats mit einer farbigen Interferenzfilterschicht, dieses Substrat, enthaltend eine farbige Interferenzfilterschicht, die Verwendung dieses Substrats als farbige Solarzelle oder als farbiges Solarmodul oder als Bestandteil hiervon sowie ein Array, umfassend mindestens zwei dieser Substrate

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3994430A (en) * 1975-07-30 1976-11-30 General Electric Company Direct bonding of metals to ceramics and metals
US4518982A (en) * 1981-02-27 1985-05-21 Motorola, Inc. High current package with multi-level leads
JPS60113931A (ja) * 1983-11-25 1985-06-20 Toshiba Corp 半導体装置
JPH0810710B2 (ja) * 1984-02-24 1996-01-31 株式会社東芝 良熱伝導性基板の製造方法
JPS6142928A (ja) * 1984-07-31 1986-03-01 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 半導体パワ−・デバイス・パツケ−ジ
DE3477531D1 (en) * 1984-11-15 1989-05-03 Fuji Electric Co Ltd Semiconductor device comprising a support body
IT1202657B (it) * 1987-03-09 1989-02-09 Sgs Microelettronica Spa Procedimento di fabbricazione di un dispositivo modulare di potenza a semiconduttore e dispositivo con esso ottenento
US5012324A (en) * 1987-07-03 1991-04-30 Doduco Gmbh And Co. Dr. Eugen Durrwachter Flat body, particularly for use as a heat sink for electronic power components
DE3813364A1 (de) * 1988-04-21 1989-11-02 Bodenseewerk Geraetetech Vorrichtung zur waermeabfuhr von bauelementen auf einer leiterplatte
DE3922485C1 (ja) * 1989-07-08 1990-06-13 Doduco Gmbh + Co Dr. Eugen Duerrwaechter, 7530 Pforzheim, De

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US5906310A (en) * 1994-11-10 1999-05-25 Vlt Corporation Packaging electrical circuits
US5938104A (en) * 1994-11-10 1999-08-17 Vlt Corporation Direct metal bonding
US6096981A (en) * 1994-11-10 2000-08-01 Vlt Corporation Packaging electrical circuits
US6159772A (en) * 1994-11-10 2000-12-12 Vlt Corporation Packaging electrical circuits
US5945130A (en) * 1994-11-15 1999-08-31 Vlt Corporation Apparatus for circuit encapsulation
US6403009B1 (en) * 1994-11-15 2002-06-11 Vlt Corporation Circuit encapsulation
US6710257B2 (en) 1994-11-15 2004-03-23 Vlt Corporation Circuit encapsulation
US5727727A (en) * 1995-02-02 1998-03-17 Vlt Corporation Flowing solder in a gap
US8587105B2 (en) 2011-09-21 2013-11-19 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
EP0468475A1 (en) 1992-01-29
KR950000203B1 (ko) 1995-01-11
EP0468475B1 (en) 1996-11-27
DE69123298T2 (de) 1997-04-24
US5216279A (en) 1993-06-01
JP2504610B2 (ja) 1996-06-05
KR920003485A (ko) 1992-02-29
DE69123298D1 (de) 1997-01-09

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