JPH0474745B2 - - Google Patents

Info

Publication number
JPH0474745B2
JPH0474745B2 JP59034103A JP3410384A JPH0474745B2 JP H0474745 B2 JPH0474745 B2 JP H0474745B2 JP 59034103 A JP59034103 A JP 59034103A JP 3410384 A JP3410384 A JP 3410384A JP H0474745 B2 JPH0474745 B2 JP H0474745B2
Authority
JP
Japan
Prior art keywords
memory
signal
access
cas
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59034103A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6041156A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS6041156A publication Critical patent/JPS6041156A/ja
Publication of JPH0474745B2 publication Critical patent/JPH0474745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Bus Control (AREA)
  • Controls And Circuits For Display Device (AREA)
JP3410384A 1983-02-25 1984-02-24 非同期制御装置 Granted JPS6041156A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8303143 1983-02-25
FR8303143A FR2541796B1 (fr) 1983-02-25 1983-02-25 Dispositif permettant de repartir le temps d'acces d'une memoire sur plusieurs utilisateurs

Publications (2)

Publication Number Publication Date
JPS6041156A JPS6041156A (ja) 1985-03-04
JPH0474745B2 true JPH0474745B2 (en, 2012) 1992-11-27

Family

ID=9286283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3410384A Granted JPS6041156A (ja) 1983-02-25 1984-02-24 非同期制御装置

Country Status (4)

Country Link
EP (1) EP0120745B1 (en, 2012)
JP (1) JPS6041156A (en, 2012)
DE (1) DE3477974D1 (en, 2012)
FR (1) FR2541796B1 (en, 2012)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2215874A (en) * 1988-03-23 1989-09-27 Benchmark Technologies Arbitration system
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3376554A (en) * 1965-04-05 1968-04-02 Digital Equipment Corp Digital computing system
JPS54530A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Reference control unit of memory
FR2406250A1 (fr) * 1977-10-17 1979-05-11 Texas Instruments France Dispositif d'acces direct a une memoire associee a un microprocesseur
JPS5939830B2 (ja) * 1979-07-18 1984-09-26 株式会社ユニバ−サル マイクロコンピユ−タのデ−タ書込・読出方式
DE2948159C2 (de) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen
JPS57111585A (en) * 1980-12-27 1982-07-12 Fujitsu Ltd Memory access system
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed

Also Published As

Publication number Publication date
DE3477974D1 (en) 1989-06-01
FR2541796B1 (fr) 1987-08-21
EP0120745B1 (en) 1989-04-26
JPS6041156A (ja) 1985-03-04
EP0120745A1 (en) 1984-10-03
FR2541796A1 (fr) 1984-08-31

Similar Documents

Publication Publication Date Title
US4623986A (en) Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle
US4698753A (en) Multiprocessor interface device
US4858107A (en) Computer device display system using conditionally asynchronous memory accessing by video display controller
JPS6242228A (ja) 表示情報処理システム
US6272583B1 (en) Microprocessor having built-in DRAM and internal data transfer paths wider and faster than independent external transfer paths
JPH0622008B2 (ja) 同期化回路
JP2001184300A (ja) データ処理プロセッサ
US4581611A (en) Character display system
JPH0474745B2 (en, 2012)
US6587932B2 (en) Processor and system for controlling shared access to a memory
EP0341670B1 (en) Processing time allocation system and method
JPH0430052B2 (en, 2012)
US6505274B2 (en) Processor and system for controlling shared access to a memory
JPH09311812A (ja) マイクロコンピュータ
JPS5965998A (ja) ダイナミツクメモリのリフレツシユ方式
JPS644187B2 (en, 2012)
JPH01131596A (ja) ビデオ更新構成体を含むコンピュータワークステーション
JPS5967585A (ja) 表示制御装置
JPS6243888A (ja) デユアルポ−トメモリ
JPS59231588A (ja) デイスプレイ装置
JP2570271B2 (ja) 半導体メモリ制御装置
JPS61208553A (ja) コンピユータ・アクセス制御方法及びコンピユータ・アクセス制御装置
JPS59106024A (ja) Ｄｍａ制御装置
JPS59219780A (ja) グラフイツクメモリ・アクセス回路
JPS635758B2 (en, 2012)

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees