JPH0457119B2 - - Google Patents

Info

Publication number
JPH0457119B2
JPH0457119B2 JP6589985A JP6589985A JPH0457119B2 JP H0457119 B2 JPH0457119 B2 JP H0457119B2 JP 6589985 A JP6589985 A JP 6589985A JP 6589985 A JP6589985 A JP 6589985A JP H0457119 B2 JPH0457119 B2 JP H0457119B2
Authority
JP
Japan
Prior art keywords
inner layer
layer printed
board
multilayer board
printed boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6589985A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61224497A (ja
Inventor
Katsunori Ariji
Yoshitomo Tsutsumi
Masamitsu Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Chemical Products Co Ltd
Original Assignee
Toshiba Chemical Products Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Chemical Products Co Ltd filed Critical Toshiba Chemical Products Co Ltd
Priority to JP6589985A priority Critical patent/JPS61224497A/ja
Publication of JPS61224497A publication Critical patent/JPS61224497A/ja
Publication of JPH0457119B2 publication Critical patent/JPH0457119B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits

Landscapes

  • Lining Or Joining Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP6589985A 1985-03-29 1985-03-29 多層板の製造方法 Granted JPS61224497A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6589985A JPS61224497A (ja) 1985-03-29 1985-03-29 多層板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6589985A JPS61224497A (ja) 1985-03-29 1985-03-29 多層板の製造方法

Publications (2)

Publication Number Publication Date
JPS61224497A JPS61224497A (ja) 1986-10-06
JPH0457119B2 true JPH0457119B2 (enrdf_load_stackoverflow) 1992-09-10

Family

ID=13300269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6589985A Granted JPS61224497A (ja) 1985-03-29 1985-03-29 多層板の製造方法

Country Status (1)

Country Link
JP (1) JPS61224497A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256696A (ja) * 1985-05-08 1986-11-14 松下電工株式会社 多層印刷配線板の製造方法
US4918812A (en) * 1988-06-29 1990-04-24 International Business Machines Corporation Processing of cores for circuit boards or cards
JP4591181B2 (ja) * 2005-04-25 2010-12-01 三菱電機株式会社 プリント配線板
JP2009181985A (ja) * 2008-01-29 2009-08-13 Sharp Corp 多層プリント配線板の製造方法および仮止め装置

Also Published As

Publication number Publication date
JPS61224497A (ja) 1986-10-06

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees