JPH0457114B2 - - Google Patents

Info

Publication number
JPH0457114B2
JPH0457114B2 JP59223709A JP22370984A JPH0457114B2 JP H0457114 B2 JPH0457114 B2 JP H0457114B2 JP 59223709 A JP59223709 A JP 59223709A JP 22370984 A JP22370984 A JP 22370984A JP H0457114 B2 JPH0457114 B2 JP H0457114B2
Authority
JP
Japan
Prior art keywords
electrode
electrodes
thin film
transistor
short
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59223709A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61100971A (ja
Inventor
Kenichi Oki
Satoru Kawai
Tomotaka Matsumoto
Yasuhiro Nasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59223709A priority Critical patent/JPS61100971A/ja
Publication of JPS61100971A publication Critical patent/JPS61100971A/ja
Publication of JPH0457114B2 publication Critical patent/JPH0457114B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP59223709A 1984-10-23 1984-10-23 薄膜トランジスタの製造方法 Granted JPS61100971A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59223709A JPS61100971A (ja) 1984-10-23 1984-10-23 薄膜トランジスタの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59223709A JPS61100971A (ja) 1984-10-23 1984-10-23 薄膜トランジスタの製造方法

Publications (2)

Publication Number Publication Date
JPS61100971A JPS61100971A (ja) 1986-05-19
JPH0457114B2 true JPH0457114B2 (cg-RX-API-DMAC7.html) 1992-09-10

Family

ID=16802432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59223709A Granted JPS61100971A (ja) 1984-10-23 1984-10-23 薄膜トランジスタの製造方法

Country Status (1)

Country Link
JP (1) JPS61100971A (cg-RX-API-DMAC7.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6486113A (en) * 1987-09-29 1989-03-30 Casio Computer Co Ltd Manufacture of thin film transistor
JPH0711642B2 (ja) * 1988-10-27 1995-02-08 シャープ株式会社 表示電極基板の製造方法
FR2662290B1 (fr) * 1990-05-15 1992-07-24 France Telecom Procede de realisation d'un ecran d'affichage a matrice active et a condensateurs de stockage et ecran obtenu par ce procede.
JP4746557B2 (ja) * 2004-10-25 2011-08-10 パイオニア株式会社 電子回路基板及びその製造方法
JP5568543B2 (ja) * 2011-12-02 2014-08-06 株式会社ジャパンディスプレイ 平面表示装置用アレイ基板の製造方法

Also Published As

Publication number Publication date
JPS61100971A (ja) 1986-05-19

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees