JPH0439789B2 - - Google Patents

Info

Publication number
JPH0439789B2
JPH0439789B2 JP59162551A JP16255184A JPH0439789B2 JP H0439789 B2 JPH0439789 B2 JP H0439789B2 JP 59162551 A JP59162551 A JP 59162551A JP 16255184 A JP16255184 A JP 16255184A JP H0439789 B2 JPH0439789 B2 JP H0439789B2
Authority
JP
Japan
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region
layer
type
buried
base region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59162551A
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English (en)
Japanese (ja)
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JPS6142166A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16255184A priority Critical patent/JPS6142166A/ja
Publication of JPS6142166A publication Critical patent/JPS6142166A/ja
Publication of JPH0439789B2 publication Critical patent/JPH0439789B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Bipolar Integrated Circuits (AREA)
JP16255184A 1984-08-01 1984-08-01 半導体注入集積論理回路装置の製造方法 Granted JPS6142166A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16255184A JPS6142166A (ja) 1984-08-01 1984-08-01 半導体注入集積論理回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16255184A JPS6142166A (ja) 1984-08-01 1984-08-01 半導体注入集積論理回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6142166A JPS6142166A (ja) 1986-02-28
JPH0439789B2 true JPH0439789B2 (enrdf_load_stackoverflow) 1992-06-30

Family

ID=15756738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16255184A Granted JPS6142166A (ja) 1984-08-01 1984-08-01 半導体注入集積論理回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS6142166A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6142166A (ja) 1986-02-28

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