JPH0434780B2 - - Google Patents

Info

Publication number
JPH0434780B2
JPH0434780B2 JP9715884A JP9715884A JPH0434780B2 JP H0434780 B2 JPH0434780 B2 JP H0434780B2 JP 9715884 A JP9715884 A JP 9715884A JP 9715884 A JP9715884 A JP 9715884A JP H0434780 B2 JPH0434780 B2 JP H0434780B2
Authority
JP
Japan
Prior art keywords
input
buffer
magnetic tape
memory
output control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9715884A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60239822A (ja
Inventor
Shigeru Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9715884A priority Critical patent/JPS60239822A/ja
Publication of JPS60239822A publication Critical patent/JPS60239822A/ja
Publication of JPH0434780B2 publication Critical patent/JPH0434780B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
JP9715884A 1984-05-15 1984-05-15 入出力バツフア制御方式 Granted JPS60239822A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9715884A JPS60239822A (ja) 1984-05-15 1984-05-15 入出力バツフア制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9715884A JPS60239822A (ja) 1984-05-15 1984-05-15 入出力バツフア制御方式

Publications (2)

Publication Number Publication Date
JPS60239822A JPS60239822A (ja) 1985-11-28
JPH0434780B2 true JPH0434780B2 (enExample) 1992-06-09

Family

ID=14184759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9715884A Granted JPS60239822A (ja) 1984-05-15 1984-05-15 入出力バツフア制御方式

Country Status (1)

Country Link
JP (1) JPS60239822A (enExample)

Also Published As

Publication number Publication date
JPS60239822A (ja) 1985-11-28

Similar Documents

Publication Publication Date Title
JPS618785A (ja) 記憶装置アクセス制御方式
US7318120B2 (en) Hardware assisted communication between processors
JPH0248747A (ja) マイクロプロセツサ
JPH0434780B2 (enExample)
JPH02114313A (ja) 高速外部記憶装置
JPS63292356A (ja) Dma制御装置
JPS63201810A (ja) 情報処理システムの時刻方式
JPS61150055A (ja) Dmaデ−タ転送方式
JPS6024666A (ja) 高速dma装置
JPH0246967B2 (enExample)
JPS5849960B2 (ja) 情報チエツク方式
JPH0235515A (ja) バス管理方法
JPS63118965A (ja) Dmaワ−ド転送方式
JPH04195234A (ja) データ転送方式
JPH01114961A (ja) ダイレクトメモリアクセス制御装置
JPS58223861A (ja) 入出力制御装置のデ−タ2重記録方式
JPH06314251A (ja) Scsiデータ転送装置
JPS59226957A (ja) デ−タ制御システム
JPH01191964A (ja) メモリバスデータ転送方法
JPH02125358A (ja) 多重バスメモリアクセス調停方式
JPS588336A (ja) デ−タ転送方法
JPS61276049A (ja) ダイレクト・メモリ・アクセス制御方式
JPH04130917A (ja) 電子ディスク装置
JPS6198437A (ja) 入出力制御方式
JPS62145345A (ja) 直接メモリアクセス間隔制御方式

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term