JPH043120B2 - - Google Patents

Info

Publication number
JPH043120B2
JPH043120B2 JP58237602A JP23760283A JPH043120B2 JP H043120 B2 JPH043120 B2 JP H043120B2 JP 58237602 A JP58237602 A JP 58237602A JP 23760283 A JP23760283 A JP 23760283A JP H043120 B2 JPH043120 B2 JP H043120B2
Authority
JP
Japan
Prior art keywords
diamond
semiconductor element
multilayer wiring
layer
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58237602A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60128697A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP58237602A priority Critical patent/JPS60128697A/ja
Publication of JPS60128697A publication Critical patent/JPS60128697A/ja
Publication of JPH043120B2 publication Critical patent/JPH043120B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
JP58237602A 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板 Granted JPS60128697A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58237602A JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58237602A JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Publications (2)

Publication Number Publication Date
JPS60128697A JPS60128697A (ja) 1985-07-09
JPH043120B2 true JPH043120B2 (cg-RX-API-DMAC7.html) 1992-01-22

Family

ID=17017750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58237602A Granted JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Country Status (1)

Country Link
JP (1) JPS60128697A (cg-RX-API-DMAC7.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181550A (ja) * 1988-01-12 1989-07-19 Toppan Printing Co Ltd 多層電子回路
JP2689986B2 (ja) * 1988-07-13 1997-12-10 富士通株式会社 電子装置
JP3309492B2 (ja) * 1993-05-28 2002-07-29 住友電気工業株式会社 半導体装置用基板
JP2004356429A (ja) * 2003-05-29 2004-12-16 Sumitomo Electric Ind Ltd サブマウントおよびそれを用いた半導体装置
JP4946502B2 (ja) * 2007-02-23 2012-06-06 株式会社ジェイテクト 回路構造

Also Published As

Publication number Publication date
JPS60128697A (ja) 1985-07-09

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