JPH043120B2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field This invention relates to a multilayer wiring board on which semiconductor elements can be mounted, and in particular, a multilayer wiring board that can efficiently dissipate heat generated by IC chips and that can be mounted with high density. The present invention relates to a multilayer wiring board capable of

(b) Prior art and its problems Recent advances in the density of integrated circuits, etc. have been remarkable.
For example, LSI for computer logic circuits used to have 100 gates/chip a few years ago.
Recently, devices with 500 to 1000 gates/chip have come into use. At the same time, the demand for high-density circuit packaging is increasing, and the mounting method that satisfies this demand has traditionally been to mount multiple 100-gate/chip LSIs on a ceramic substrate with multilayer wiring. So much so that it has been done.

However, when using a conventional Al ₂ O ₃ ceramic substrate, it is relatively thick and the Al ₂ O ₃
Due to the poor thermal conductivity of ceramics, the heat generated by IC chips cannot be efficiently dissipated when multi-layered, and this has been an impediment to higher density circuit packaging. .

In addition, instead of the Al ₂ O ₃ substrate, materials such as an Al substrate whose surface is anodized, an enameled Fe plate, and a composite material of an alumina substrate and a highly thermally conductive metal such as Cu or Mo have been devised.

Among the above materials, alumite substrates have insufficient heat resistance and the base metal Al has a high coefficient of thermal expansion, making it difficult to mount large elements or enlarge the circuit itself.

In addition, enameled Fe plates are not only unsatisfactory in terms of heat dissipation and thermal expansion properties, but also have a large thermal resistance because the enamel layer as an insulating layer has to be several tens of micrometers thick. It has disadvantages such as:

Furthermore, in the case of a composite substrate of alumina and metal, it is difficult to reduce the thickness of alumina, which inherently has low thermal conductivity, to 0.1 μm or less, and a fully satisfactory substrate has not been obtained.

On the other hand, BeO and BeO-containing SiC have been put into practical use or developed as ceramic substrates to overcome these drawbacks, but since they both use toxic BeO, their industrial use will be severely restricted in the future. Also, it is expensive in terms of cost. In addition, it is difficult to improve the precision of the method due to warping of the ceramic substrate itself, and it is extremely difficult to manufacture large substrates, which are expected to increase in number in the future.

As a way to overcome the above drawbacks, W.
A thin layer of ceramic or glass component materials such as Al ₂ O ₃ is applied to the surface of high thermal conductivity or low thermal expansion metals such as Mo, CuW alloys, CuMo alloys, and other composite metals of Cu and Mo or FeNi alloys. Layer coated materials have been devised and used effectively.

However, as the frequencies of semiconductor devices become higher, such materials also have the disadvantage that the thin ceramic layer forms a capacitor between the base metal and the conductive circuit formed on the ceramic layer, which adversely affects its electrical properties. I started coming. This is due to the high dielectric constant of the thin ceramic layer used, and the typical ceramic Al ₂ O ₃ has a high dielectric constant of 1 MHz.
8.5 to 10.0, and in the range of 10 μm or less, where thermal resistance can be ignored, when a potential difference occurs in a conductor circuit on a thin ceramic layer, it acts as a capacitor through this ceramic layer, and when high-frequency signals propagate. This disturbs the current waveform and makes it impossible to function as a circuit board. To overcome this drawback, it is necessary to form the coating ceramic layer to a thickness of 20 to 30 .mu.m.

However, providing a ceramic layer with a thickness of 20 to 30 .mu.m not only increases the cost significantly, but also causes the thermal resistance to become non-negligible, resulting in the loss of the characteristics of a highly heat-dissipating circuit board.

The object of the present invention is to solve these problems and provide a multilayer wiring circuit board that can mount a large number of high-frequency semiconductor elements, has good thermal conductivity, and can be mounted at high density. be.

(C) Means for Solving the Problems In order to achieve the above object, the present invention coats a metal substrate with diamond, a pseudo-diamond-like carbon film, or a mixture thereof as an electrically insulating coating layer, and In a multilayer wiring board in which a multilayer circuit pattern is formed on an insulating coating layer, the interlayer insulating layer of the multilayer circuit pattern is formed of diamond, a pseudo-diamond-like carbon film, or a mixture thereof.

Hereinafter, the content of the present invention will be specifically explained with reference to the accompanying drawings.

The figure shows an example of a semiconductor device using the circuit board of the present invention, in which 1 is a metal substrate, 2 is an electrically insulating coating layer coated on the surface thereof, 3 is a multilayer circuit pattern,
4 is an interlayer insulating layer of the multilayer circuit pattern 3, 5 is a semiconductor element, and 6 is a bonding wire.

The above metal substrate 1 has a thermal expansion coefficient of 4.5 to 9.0×
10 ⁻⁶ cm/cm° C. and is formed of one metal material or composite metal material selected from the following groups a to c, which are materials with good thermal conductivity.

a CuW alloy, CuMo alloy, CuWMo alloy b W, Mo, Kovar, 42 alloy c W, Mo, Kovar or 42 alloy,
Composite gold layer with Cu, Al or Ni The thermal expansion coefficient of the material forming the metal substrate 1 was selected as described above because the thermal expansion coefficient of the crystal of the mounted semiconductor element 5 (Si: 4.0×10 ^-6 cm /cm℃, GaAs:
6.7×10 ^-6 cm/cm°C) to reduce the influence of stress caused by thermal expansion mismatch.

In addition, the materials in groups a to c were selected because these materials have the above-mentioned thermal expansion characteristics, as well as to increase the thermal conductivity of the metal substrate 1 as much as possible and to dissipate heat generated in the semiconductor element 5. This is to improve the

Next, the electrically insulating coating layer 2 and the interlayer insulating layer 4 are made of diamond having a dielectric constant of 2.5 or more and 8 or less.
A thin layer of 0.5 to 20 μm of pseudo-diamond-like carbon or a mixture thereof,
The metal substrate 1 is coated by vapor phase deposition.

As the vapor phase deposition method, PVD method or CVD method is preferable. These two methods each have their own advantages and disadvantages, but basically they are methods in which hydrocarbon gas such as methane is effectively decomposed using heat, magnetic field, high frequency, DC electric field, etc., and then the decomposition is deposited on the substrate. By controlling the deposition conditions such as the deposition temperature and the output of the magnetic field or electric field, the composition of the coating layer 2 and the interlayer insulating layer 4 can be changed from diamond to pseudo-diamond-like carbon or a mixture thereof (pseudo-diamond-like carbon). It is possible to freely deposit a carbon film with fine diamond particles dispersed in it.

Further, the reason why the dielectric constant of the coating layer 2 and the interlayer insulating layer 4 was selected to be 2.5 or more and 5.5 or less is as follows.

As is well known, the dielectric constants of the coating layer 2 and the interlayer insulating layer 4 are determined by the composition of the coating material. The compositions of the coating layer 2 and the interlayer insulating layer 4 in this invention can be controlled by changing the deposition conditions as described above. I was thinking of controlling it as needed. Regarding this point, the inventors conducted detailed experiments and surprisingly found that the dielectric constant of the coating layer 2 and the interlayer insulating layer 4 could be controlled within the range of 2.5 to 5.5. Natural diamond has a dielectric constant of 5.5, and it is unclear why the coating layer synthesized by vapor phase deposition has such a wide range of values.

The reason why the thickness of the coating layer 2 and the interlayer insulating layer 4 is set to 0.5 or more and 20 μm or less is as follows.
In other words, no matter what composition of film is used, the thickness is 0.5 μm.
Below this, the capacitance as a capacitor becomes large, which impairs the effect of the present invention. Moreover, if the thickness is 20 μm or more, it is not only uneconomical because it takes time to form, but also there are problems such as peeling due to internal stress, which is a characteristic of diamond or pseudo-diamond-like carbon films.

Next, the circuit pattern 3 is made of Cu, Al,
It is made of any one of Ni, Ag, Au, and AgPb alloys, or a combination thereof, and can be formed by any method such as a thin film method, a thick film method, or a transfer method. These materials and forming methods are appropriately selected depending on usage, cost, etc.

(d) Example As a metal substrate, the thermal expansion coefficient is 6.5×10 ^-6 cm/
Thickness 1.0 containing 15wt% Cu to make cm℃
After manufacturing CuW alloy plates with dimensions of 100 mm and 100 mm by a powder sintering method, a plasma decomposition vapor deposition method was performed to form a diamond layer on the surface using the following method.

That is, the substrate was placed in a vacuum container, heated to 450℃ using infrared heating, and CH ₄ gas was heated at 35c.c./min.
While supplying the gas into the container, the total gas pressure was adjusted to 5×10 ^-3 . Plasma was then generated using a 5-turn coil installed in the container using a high frequency of 13.56 MHz, and evaporation was performed for 5 hours to obtain a diamond film with a thickness of 3 μm. When the obtained film was subjected to reflected electron beam diffraction, it was found that the deposited film was composed of both amorphous and crystal parts.
In addition, when we measured the dielectric constant of the same film, it was 4.9 at 1MHz.
It was hot.

Furthermore, using a metal mask manufactured based on the required circuit pattern, a 3 μm thick Cu circuit pattern was formed by RF ion plating.
Thereafter, a diamond film with a thickness of 3 μm was formed as an interlayer insulating layer using the method described above, and the diamond film was etched using a partial ion etching method in the necessary portions of the through holes to form through holes. This through hole was coated with 3 μm of Cu using the PF ion plating method using a metal mask.
Furthermore, a Cu circuit pattern was formed using the method described above.

This process of forming an interlayer insulating film, forming a through hole, and forming a circuit pattern was repeated to obtain a three-layer circuit board.

The portions of the circuit pattern on the top surface of this circuit board that were required for wire bonding and die bonding were coated with Ni to a thickness of 2 μm, and further coated with Au to a thickness of 1 μm.

Six GaAsFET elements are placed on the above circuit board.
After die bonding using AuSn alloy, wire bonding was performed using Au wire, and a chip capacitor was mounted.

The multi-chip FET manufactured in this way is
It was possible to operate in the high frequency range of 10GHz or higher, and the total amount of heat generated was 30W.

(E) Effect As described above, the present invention provides a method in which both the electrically insulating coating layer covering the metal substrate and the interlayer insulating layer of the circuit pattern are formed of diamond, pseudo-diamond-like carbon film, or a mixture thereof. Therefore, even if these coating layers and interlayer insulating layers are formed sufficiently thin, their dielectric constants can be controlled within the range of 2.5 to 5.5. Therefore, it is possible to obtain a multilayer wiring board for mounting semiconductor elements, which has low thermal resistance and has less influence on high frequency signals.

[Brief explanation of drawings]

The drawing is an enlarged sectional view of a semiconductor device using the substrate of the present invention. DESCRIPTION OF SYMBOLS 1...Metal substrate, 2...Electric insulation coating layer, 3...
...Circuit pattern, 4...Interlayer insulating layer, 5...Semiconductor element, 6...Bonding wire.

Claims (1)

[Claims] 1. A multilayer wiring for mounting a semiconductor element, in which a metal substrate is coated with diamond, a pseudo-diamond-like carbon film, or a mixture thereof as an electrically insulating coating layer, and a multilayer circuit pattern is formed on the electrically insulating coating layer. 1. A multilayer wiring board for mounting a semiconductor element, characterized in that an interlayer insulating layer of a multilayer circuit pattern is formed of diamond, a pseudo-diamond-like carbon film, or a mixture thereof. 2 The thermal expansion coefficient of the metal substrate is 4.5 to 9.0×10 ^-6 cm/
Claim 1 characterized in that the temperature is cm°C.
A multilayer wiring board for mounting a semiconductor element as described in 2. 3. The multilayer wiring board for mounting a semiconductor element according to claim 1, wherein the metal substrate is made of any one material selected from the following groups a to c. a CuW alloy, CuMo alloy, CuWMo alloy b W, Mo, Kovar, 42 alloy c W, Mo, Kovar or 42 alloy,
Alloyed layer with Cu, Al or Ni. 4. Claim 1, characterized in that the electrically insulating coating layer and the interlayer insulating layer are formed by vapor deposition to a thickness of 0.5 μm or more and 20 μm or less, and have a dielectric constant of 2.5 or more and 5.5 or less. A multilayer wiring board for mounting a semiconductor element as described in . 5. The multilayer wiring board for mounting a semiconductor element according to claim 1, wherein the semiconductor element to be mounted is Si or GaAs.