JPS61111598A - Manufacture of glass ceramic multilayer circuit board - Google Patents
Manufacture of glass ceramic multilayer circuit boardInfo
- Publication number
- JPS61111598A JPS61111598A JP21461084A JP21461084A JPS61111598A JP S61111598 A JPS61111598 A JP S61111598A JP 21461084 A JP21461084 A JP 21461084A JP 21461084 A JP21461084 A JP 21461084A JP S61111598 A JPS61111598 A JP S61111598A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- ceramic multilayer
- circuit board
- nitride
- multilayer substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は微細パターンの形成が可能で且つ放熱性の良い
ガラスセラミックス多層基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a glass-ceramic multilayer substrate that allows the formation of fine patterns and has good heat dissipation.
電算機の高速化と大容量化に対応してICやLSIなど
の半導体装置はこれを構成する単位素子が微少化され、
また各素子間を回路接続する導体パターン幅が縮小され
ているが、一方では素子数が一段と増加したVLSIが
実用化されている。In response to the increasing speed and capacity of computers, the unit elements that make up semiconductor devices such as ICs and LSIs have been miniaturized.
Further, while the width of the conductor pattern for circuit connection between each element has been reduced, on the other hand, VLSI with a further increase in the number of elements has been put into practical use.
またこれらの半導体装置のプリント配線基板への搭載法
も進歩しており、従来はIC,LSIなどの半導体素子
を個々にパッケージング外装を施し、これをプリント配
線基板に設けられているスルーホール或いはパッドに溶
着する搭載方法がとられていたが、現在ではセラミック
からなるプリント配線基板に複数個のLSIチップを装
着し、そのまヽで或いは一括してパッケージングし、こ
れを取替単位としてプリント配線基板に搭載するLSI
モジュールの方向に移行しつつある。In addition, the method of mounting these semiconductor devices onto printed wiring boards has also progressed. Conventionally, semiconductor elements such as ICs and LSIs were individually packaged and packaged using through-holes provided on the printed wiring board. Previously, the mounting method was to weld them to the pads, but now multiple LSI chips are mounted on a ceramic printed wiring board, packaged as is or in bulk, and printed as a replacement unit. LSI mounted on wiring board
We are moving towards modules.
従来の技術
複数個のLSIを装着するセラミック回路基板の必要条
件として次の点が挙げられる。2. Description of the Related Art The following points are necessary for a ceramic circuit board on which a plurality of LSIs are mounted.
■多層構成で熱伝導の良いこと。■Multi-layer structure with good heat conduction.
■微細な導体パターンの形成が可能なこと。■It is possible to form fine conductor patterns.
■信号の伝送特性が優れていること。■Excellent signal transmission characteristics.
すなわちLSIは多数の端子数を備えて形成されている
が、か\るLSIが複数個装着されるためにセラミック
回路基板の裏面に設けたリードピンへ回路接続する配線
数は真人なものとなる。That is, an LSI is formed with a large number of terminals, but since a plurality of such LSIs are mounted, the number of wires connected to the lead pins provided on the back surface of the ceramic circuit board becomes substantial.
例えば10cn+角の回路基板に2000〜3000本
のり−ドビンの装着が予定されている。For example, it is planned that 2,000 to 3,000 glue dowels will be attached to a 10 cm square circuit board.
そのために回路基板は多層構造をとることが必要であり
、また導体パターンの線幅が極めて狭いことが、必要と
なる。Therefore, it is necessary for the circuit board to have a multilayer structure, and it is also necessary that the line width of the conductor pattern be extremely narrow.
またか\る多層配線は信号線、電源線などによって構成
されているが、信号の周波数が高いために層間或いは配
線間の漏話(クロストーク)や信号の遅延が少ないこと
が必要であり。Furthermore, such multilayer wiring is made up of signal lines, power supply lines, etc., and because the signal frequency is high, it is necessary that crosstalk between layers or wiring and signal delay be small.
また配線の発熱を抑制するために配線パターンは抵抗が
少なく、また回路基板は熱伝導のよい材料で構成されて
いることが必要である。Furthermore, in order to suppress heat generation in the wiring, the wiring pattern must have low resistance, and the circuit board must be made of a material with good thermal conductivity.
然し、かかる条件を充分に満たしfこセラミック回路基
板は未だ実用化されていない。However, a ceramic circuit board that fully satisfies these conditions has not yet been put into practical use.
従来、かかる目的に使用する回路基板としてガラスセラ
ミックス多層基板が実用化されている。Conventionally, glass ceramic multilayer substrates have been put into practical use as circuit boards used for such purposes.
すなわち厚さ約200μmのガラスセラミックスグリン
シートの上に銅(Cu )或いは金(Au )を主構成
材とする導電性ペーストをスクリーン印刷法で塗布して
導体パターンの形成を行うと共に必要位置にバイアホー
ルを形成し、かかる複数のグリンシートを積層して焼成
し、一体化するグリンシート積層法で形成されていた。That is, a conductive paste mainly composed of copper (Cu) or gold (Au) is applied onto a glass-ceramic green sheet approximately 200 μm thick by screen printing to form a conductor pattern, and vias are formed at the required positions. It was formed by a green sheet lamination method in which holes are formed, a plurality of such green sheets are stacked, fired, and integrated.
ここでガラスセラミックスが使用される理由は誘電率が
5程度と従来のアルミナと較べて約2と少なく漏話が押
さえられること、およびA u + Cuなど導体抵抗
の低い金属が使用できることによる。The reason why glass ceramics are used here is that the dielectric constant is about 5, which is about 2, which suppresses crosstalk compared to conventional alumina, and that metals with low conductor resistance, such as A u + Cu, can be used.
すなわち従来のアルミナ基板の焼成温度は約1600°
Cと高く、Au、Cuなど融点が1000°C付近の金
属元素を使用することができない。In other words, the firing temperature of conventional alumina substrates is approximately 1600°.
C, and metallic elements with melting points near 1000°C, such as Au and Cu, cannot be used.
一方ガラスセラミックスは構成するガラスの種類により
異なるが焼成温度は900〜1000℃であり、そのた
めAuJPCuペーストを使用することができ低抵抗な
導体パターンを形成することができる。On the other hand, the firing temperature of glass ceramics is 900 to 1000° C., although it varies depending on the type of glass used, so AuJPCu paste can be used and a conductive pattern with low resistance can be formed.
然し、このようにして作られた多層基板は導体パターン
がスクリーン印刷法で形成されているためにパターン幅
を70μm以下にすることは困難であり、またバイアホ
ールも80μmが限界とされていた。However, since the conductor patterns of the multilayer substrate made in this manner are formed by screen printing, it is difficult to reduce the pattern width to 70 μm or less, and the limit for via holes is 80 μm.
このように微細パターンの形成が必要であるに拘わらず
充分に目的が達成されていない。As described above, although formation of fine patterns is necessary, the purpose has not been fully achieved.
本発明の目的は熱伝導率のよい基板材料を用い、パター
ン幅の狭い配線パターンを形成することにより高密度実
装に適した回路基板を提供するにある。An object of the present invention is to provide a circuit board suitable for high-density packaging by using a substrate material with good thermal conductivity and forming a narrow wiring pattern.
上記の問題点はグリンシート積層法により形成したガラ
スセラミックス多層基板上に金属蒸着膜を用いて導体パ
ターンを、また窒化物を層間絶縁層に用いて多層回路を
形成することを特徴とするガラスセラミックス多層基板
の製造方法により達成することができる。The above problem is solved by glass ceramics, which is characterized by forming a conductor pattern using a metal vapor deposition film on a glass ceramic multilayer substrate formed by the green sheet lamination method, and forming a multilayer circuit using nitride as an interlayer insulating layer. This can be achieved by a method for manufacturing a multilayer substrate.
本発明はLSIモジュールに使用されるセラミック回路
基板の必要条件を仔細に検討すると多層構成をとる各層
の総てに必ずしも微細パターンを必要としないことから
従来の基板をそのまま使用し、微細パターンを必要とす
る上部層を窒化物で層絶縁すると共に蒸着膜で配線パタ
ーンを形成して微細パターンを備えた回路基板を実現す
るものでる。A detailed study of the requirements for a ceramic circuit board used in an LSI module reveals that the present invention does not necessarily require a fine pattern in each layer of a multilayer structure, so the present invention uses a conventional board as is and does not require a fine pattern. The upper layer is insulated with nitride, and a wiring pattern is formed with a vapor-deposited film to realize a circuit board with a fine pattern.
すなわち多層基板の中央部に配置される電5IiJやア
ース層はそのパターンが微細であることを必要としない
ことから従来のグリンシート積層法で形成し、この上に
形成される信号層を本発明に係る窒化物で層間絶縁する
と共に蒸着膜で微細パターンを形成するものである。In other words, the electrical and ground layers arranged in the center of the multilayer board do not need to have fine patterns, so they are formed by the conventional green sheet lamination method, and the signal layer formed thereon is formed using the present invention. The nitride is used for interlayer insulation, and the deposited film is used to form a fine pattern.
ここで本発明において層間絶縁に使用する窒化物は窒化
アルミニウム(AI N)或いは窒化硼素(BN)であ
り、一方金属蒸着膜の材料は金(AU)或いは銅(Cu
)であって、後者は従来のパターン形成材料と変わら
ない。Here, in the present invention, the nitride used for interlayer insulation is aluminum nitride (AIN) or boron nitride (BN), while the material of the metal vapor deposition film is gold (AU) or copper (Cu).
), the latter being no different from conventional patterning materials.
AI NやBNは熱伝導率が大きく、誘電率も比較的少
なくまた化学的に安定な化合物であるが、これを従来よ
り層絶縁に使用されている酸化物と比較すると次のよう
になる。AlN and BN are chemically stable compounds that have high thermal conductivity, relatively low dielectric constant, and are compared with oxides conventionally used for layer insulation.
表
このように熱伝導率は従来品と較べてもかに高く2.そ
のため放熱効果が優れ、またBNは誘電率が少ないので
静電誘導が少なく従って漏話を抑制することができる。As shown in the table, the thermal conductivity is much higher than that of conventional products.2. Therefore, the heat dissipation effect is excellent, and since BN has a low dielectric constant, there is little electrostatic induction, so crosstalk can be suppressed.
次に化学的安定性についてAI Nは1700℃では酸
化が進行するもの\、1200°Cの加熱では掻く僅か
しか酸化が進行せず、またBNはツ00 ’Cまでの温
度では安定であり、980℃から酸(ヒが進行する(C
ampbell著 tligh−Temperatur
e Materals andTechnology
13.3.l、 243p )。Next, regarding chemical stability, AI N undergoes oxidation at 1700°C, but oxidation progresses only slightly when heated to 1200°C, and BN is stable at temperatures up to 00'C. Acid (H) progresses from 980℃ (C
tligh-Temperature by ampbell
e Materials and Technology
13.3. l, 243p).
ここで半導体装置は信頼性保持のため85“Cを最高使
用温度として保持されるので、これらの窒化物は安定し
て使用し得ると言える。Here, since the semiconductor device is maintained at a maximum operating temperature of 85"C to maintain reliability, it can be said that these nitrides can be used stably.
本発明はグリンシート積層法により形成したガラスセラ
ミックス多層基板を基板とし、この上に多層回路を形成
するものである。The present invention uses a glass-ceramic multilayer substrate formed by the green sheet lamination method as a substrate, and a multilayer circuit is formed thereon.
以下多層回路の形成法を実施例について説明する。Hereinafter, a method for forming a multilayer circuit will be described with reference to an embodiment.
実施例1
ガラスセラミック単層の厚さ約200 μm + C
u導体層の厚さ約25μmで201構成で形成されてい
るガラスセラミックス多層基板上にCuをマスク蒸着し
て導体パターンの形成を行い、次にこの上にスパッタ法
によりAI N層間絶縁層を形成し、写真食刻技術(ホ
トリソグラフィ)を用いてバイアホールを形成し、これ
を繰り返して5層よりなる多層回路を形成した。Example 1 Glass ceramic single layer thickness approximately 200 μm + C
A conductor pattern is formed by vapor depositing Cu using a mask on a glass ceramic multilayer substrate formed in a 201 configuration with a U conductor layer thickness of approximately 25 μm, and then an AI N interlayer insulating layer is formed on this by sputtering. Then, via holes were formed using photolithography, and this process was repeated to form a multilayer circuit consisting of five layers.
ここでスパッタ条件としてはホントプレスで形成したA
t N円板を対極とし、アルゴン(Ar )ガスの真空
度が10−’ 〜10″″’ Toorで行い、0.5
pmの厚さに形成した。Here, the sputtering conditions are A
The test was carried out using a tN disk as the counter electrode and the degree of vacuum of argon (Ar) gas was 10-' to 10'''Toor.
It was formed to a thickness of pm.
またCu4体パターンの輻およびバイアホールの径は共
に20IImである。Further, the radius of the Cu4 body pattern and the diameter of the via hole are both 20 IIm.
このようにして形成した多層基板はLSIを装着するセ
ラミック回路基板の必要条件を満足し、70ps/am
の伝送遅延時間を達成することができた。The multilayer board thus formed satisfies the requirements for a ceramic circuit board on which an LSI is mounted, and has a speed of 70 ps/am.
It was possible to achieve a transmission delay time of .
実施例2
ガラスセラミックス基板の厚さ200μm、Au導体層
の厚さ約25μmで20層構成のガラスセラミックス基
板の上にAuをマスク蒸着して導体パターンの形成を行
い、次にこの上に化学気相成長法(CVr)法)により
BNからなる層間絶縁層を形成し、写真食刻波jrlj
を用いてバイアホールを形成し、これを繰り返して5層
よりなる多層回路を形成した。Example 2 A conductive pattern was formed by depositing Au using a mask on a glass ceramic substrate with a 20-layer structure in which the glass ceramic substrate had a thickness of 200 μm and the Au conductor layer had a thickness of about 25 μm, and then a conductive pattern was formed on this by chemical vapor deposition. An interlayer insulating layer made of BN is formed by a phase epitaxy (CVr) method, and a photo-etched wave jrlj
A via hole was formed using the same method, and this process was repeated to form a multilayer circuit consisting of five layers.
ここでBNを形成するCVD条件は反応ガスとして塩化
硼素(BCl2)と塩化アンモン(NH4C1)の混合
ガスを使用し、ガスの流速を毎分5リツトルに調節し、
700°Cの温度で反応させ、基板上にBNを成長させ
た。Here, the CVD conditions for forming BN are as follows: A mixed gas of boron chloride (BCl2) and ammonium chloride (NH4C1) is used as the reaction gas, and the gas flow rate is adjusted to 5 liters per minute.
The reaction was carried out at a temperature of 700°C to grow BN on the substrate.
この場合の成長速度は約0.25μm/Hであり、この
方法で0.2μmの絶縁層を形成した。The growth rate in this case was about 0.25 μm/H, and an insulating layer of 0.2 μm was formed using this method.
またAug体パターンの幅およびバイアポールの径は共
に20μmである。Further, the width of the Aug body pattern and the diameter of the via pole are both 20 μm.
このようにして形成したセラミック多層基板はLSIを
装着するセラミック回路基板の必要条件を満足すると共
に70PS/cmの伝送遅延時間を達成することができ
た。The ceramic multilayer board thus formed satisfied the requirements for a ceramic circuit board on which an LSI is mounted, and was also able to achieve a transmission delay time of 70 PS/cm.
以上説明したように従来のガラスセラミックス多層基板
の上に金属蒸着膜を用いて導体パターンをまた窒化物を
用いて層間絶縁層を形成する木発明の実施により、熱伝
導が良くまた?AJ細な導体パターンを備えた多層基板
を作ることができる。As explained above, by implementing the invention in which a conductor pattern is formed using a metal vapor deposited film and an interlayer insulating layer is formed using nitride on a conventional glass-ceramic multilayer substrate, heat conduction is improved. AJ: Multilayer substrates with fine conductor patterns can be made.
Claims (5)
ックス多層基板上に金属蒸着膜を用いて導体パターンを
、また窒化物を層間絶縁層に用いて多層回路を形成する
ことを特徴とするガラスセラミックス多層基板の製造方
法。(1) A glass ceramic multilayer substrate formed by a green sheet lamination method, on which a conductor pattern is formed using a metal vapor deposition film and a multilayer circuit is formed using nitride as an interlayer insulating layer. manufacturing method.
徴とする特許請求の範囲第1項記載のガラスセラミック
ス多層基板の製造方法。(2) The method for manufacturing a glass-ceramic multilayer substrate according to claim 1, wherein the nitride is made of aluminum nitride.
特許請求の範囲第1項記載のガラスセラミックス多層基
板の製造方法。(3) The method for manufacturing a glass-ceramic multilayer substrate according to claim 1, wherein the nitride is made of boron nitride.
とする特許請求の範囲第1項記載のガラスセラミックス
多層基板の製造方法。(4) The method for manufacturing a glass-ceramic multilayer substrate according to claim 1, wherein the constituent material of the metal vapor deposited film is made of copper.
とする特許請求の範囲第1項記載のガラスセラミックス
多層基板の製造方法。(5) The method for manufacturing a glass-ceramic multilayer substrate according to claim 1, wherein the constituent material of the metal vapor deposited film is made of gold.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21461084A JPS61111598A (en) | 1984-10-13 | 1984-10-13 | Manufacture of glass ceramic multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21461084A JPS61111598A (en) | 1984-10-13 | 1984-10-13 | Manufacture of glass ceramic multilayer circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61111598A true JPS61111598A (en) | 1986-05-29 |
JPS6355238B2 JPS6355238B2 (en) | 1988-11-01 |
Family
ID=16658566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21461084A Granted JPS61111598A (en) | 1984-10-13 | 1984-10-13 | Manufacture of glass ceramic multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61111598A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61163696A (en) * | 1985-01-11 | 1986-07-24 | 日本特殊陶業株式会社 | Multilayer circuit board |
JPS6273799A (en) * | 1985-09-27 | 1987-04-04 | 日本電気株式会社 | Multilayer ceramic circuit substrate |
JPS6327094A (en) * | 1986-07-18 | 1988-02-04 | 富士通株式会社 | Manufacture of ceramic substrate for optical transmission |
JP2006500783A (en) * | 2002-09-27 | 2006-01-05 | メドトロニック ミニメド インコーポレイテッド | Multilayer board |
US7514791B2 (en) | 2002-09-27 | 2009-04-07 | Medtronic Minimed, Inc. | High reliability multilayer circuit substrates |
US8003513B2 (en) | 2002-09-27 | 2011-08-23 | Medtronic Minimed, Inc. | Multilayer circuit devices and manufacturing methods using electroplated sacrificial structures |
-
1984
- 1984-10-13 JP JP21461084A patent/JPS61111598A/en active Granted
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61163696A (en) * | 1985-01-11 | 1986-07-24 | 日本特殊陶業株式会社 | Multilayer circuit board |
JPH0416039B2 (en) * | 1985-01-11 | 1992-03-19 | Ngk Spark Plug Co | |
JPS6273799A (en) * | 1985-09-27 | 1987-04-04 | 日本電気株式会社 | Multilayer ceramic circuit substrate |
JPH0452000B2 (en) * | 1985-09-27 | 1992-08-20 | Nippon Electric Co | |
JPS6327094A (en) * | 1986-07-18 | 1988-02-04 | 富士通株式会社 | Manufacture of ceramic substrate for optical transmission |
JP2006500783A (en) * | 2002-09-27 | 2006-01-05 | メドトロニック ミニメド インコーポレイテッド | Multilayer board |
US7514791B2 (en) | 2002-09-27 | 2009-04-07 | Medtronic Minimed, Inc. | High reliability multilayer circuit substrates |
US7659194B2 (en) | 2002-09-27 | 2010-02-09 | Medtronic Minimed, Inc. | High reliability multilayer circuit substrates and methods for their formation |
US7781328B2 (en) | 2002-09-27 | 2010-08-24 | Medtronic Minimed, Inc. | Multilayer substrate |
US8003513B2 (en) | 2002-09-27 | 2011-08-23 | Medtronic Minimed, Inc. | Multilayer circuit devices and manufacturing methods using electroplated sacrificial structures |
JP2009246401A (en) * | 2003-09-26 | 2009-10-22 | Medtronic Minimed Inc | Method of forming highly reliable multi-layer circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS6355238B2 (en) | 1988-11-01 |
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