JPH11330292A - Multilayer substrate - Google Patents
Multilayer substrateInfo
- Publication number
- JPH11330292A JPH11330292A JP12715698A JP12715698A JPH11330292A JP H11330292 A JPH11330292 A JP H11330292A JP 12715698 A JP12715698 A JP 12715698A JP 12715698 A JP12715698 A JP 12715698A JP H11330292 A JPH11330292 A JP H11330292A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electronic circuit
- layer
- conductor
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子回路の高密度
化、小型化に適した多層基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer substrate suitable for increasing the density and reducing the size of an electronic circuit.
【０００２】[0002]
【従来の技術】従来の電子回路用基板には、樹脂材料や
セラミック材料が用いられ、専ら基板の片面上に回路を
形成することについて研究開発がなされてきた。2. Description of the Related Art Resin materials and ceramic materials have been used for conventional electronic circuit substrates, and research and development have been conducted exclusively on forming circuits on one side of the substrate.
【０００３】しかし、樹脂基板やセラミック基板には、
次の問題点がある。 (i) 樹脂基板やセラミック基板は、熱伝導性が悪いた
め、電子回路からの発熱を十分に放熱することができ
ず、電子回路に不具合をもたらす恐れがある。 (ii)樹脂基板やセラミック基板は、強度が小さいため、
耐振性に問題がある。 (iii) 樹脂基板は、高温で接着強度が大幅に低下する。 (iv)樹脂基板は、ベアチップのダイレクトボンディング
が樹脂材料との熱膨張係数の差により困難である。 (v) セラミック基板は、焼結後の寸法誤差やソリの発生
により、大型基板の作製が難しい。 (vi)樹脂基板及びセラミック基板は、高周波における耐
ノイズ性が悪く、特にクロストーク（平行した信号線間
で発生するノイズ）が問題となる。 (vii) 基板の片面に電子回路を形成する場合は、部品等
の実装に制約があるため、電子機器の小型化が難しい。However, resin substrates and ceramic substrates have
There are the following problems. (i) Since the resin substrate and the ceramic substrate have poor thermal conductivity, heat generated from the electronic circuit cannot be sufficiently dissipated, which may cause a failure in the electronic circuit. (ii) Resin substrates and ceramic substrates have low strength,
There is a problem in vibration resistance. (iii) The adhesive strength of the resin substrate is significantly reduced at high temperatures. (iv) In a resin substrate, direct bonding of a bare chip is difficult due to a difference in thermal expansion coefficient from a resin material. (v) It is difficult to produce large substrates for ceramic substrates due to dimensional errors and warpage after sintering. (vi) The resin substrate and the ceramic substrate have poor noise resistance at high frequencies, and particularly cause crosstalk (noise generated between parallel signal lines). (vii) When an electronic circuit is formed on one side of a substrate, it is difficult to reduce the size of the electronic device because there are restrictions on mounting components and the like.
【０００４】[0004]
【発明が解決しようとする課題】そこで、本発明では、
上記の欠点を解消し、基板の放熱を容易にし、所定の耐
振性を満たす基板強度を有し、電子回路の高密度化、小
型化を可能にした多層基板を提供しようとするものであ
る。Therefore, in the present invention,
An object of the present invention is to provide a multilayer board which solves the above-mentioned drawbacks, facilitates heat radiation of the board, has a board strength satisfying a predetermined vibration resistance, and enables high density and miniaturization of an electronic circuit.
【０００５】[0005]
【課題を解決するための手段】本発明は、次の手段を採
用することにより、上記の課題の解決に成功したもので
ある。 (1) 高熱伝導性及び低膨張性を有する基板の両面に、絶
縁体層及び導体層を必要な層数だけ繰り返して積層し、
絶縁体層及び／又は導体層をエッチングして所定の電子
回路パターンを形成してなることを特徴とする電子回路
用多層基板。SUMMARY OF THE INVENTION The present invention has succeeded in solving the above-mentioned problems by employing the following means. (1) On both sides of a substrate having high thermal conductivity and low expansion property, the required number of insulating layers and conductor layers are repeatedly laminated,
A multilayer substrate for an electronic circuit, wherein a predetermined electronic circuit pattern is formed by etching an insulator layer and / or a conductor layer.
【０００６】(2) 前記電子回路パターンに対応する前記
基板に予め穴を開け、前記絶縁体層及び前記導体層を積
層し、前記穴に導体を充填することにより、前記基板の
両面の前記導体層を相互に接続して電子回路を形成して
なることを特徴とする上記(1) 記載の電子回路用多層基
板。(2) A hole is formed in the substrate corresponding to the electronic circuit pattern in advance, the insulator layer and the conductor layer are laminated, and the hole is filled with a conductor, whereby the conductor on both surfaces of the substrate is filled. The multilayer substrate for an electronic circuit according to the above (1), wherein the layers are connected to each other to form an electronic circuit.
【０００７】(3) 前記絶縁体層と前記導体層との間に、
両者の密着性を確保するための薄い金属層を設けてなる
ことを特徴とする上記(1) 又は(2) 記載の電子回路用多
層基板。(3) Between the insulator layer and the conductor layer,
The multilayer board for an electronic circuit according to the above (1) or (2), further comprising a thin metal layer provided for ensuring adhesion between the two.
【０００８】図１は、本発明の１具体例を示した多層基
板の断面図である。高熱伝導性及び低膨張性を有する基
板１に対し、電子回路パターンに対応する面間接続穴４
を予め開けておき、基板１の両面に絶縁体層２及び導体
層３を積層し、絶縁体層２及び／又は導体層３をエッチ
ングして所定の電子回路パターンを形成し、基板１の両
面の導体層３を接続する必要のある面間接続穴４には導
体を充填し、接続が不用の面間接続穴４はレジスト材５
で封鎖する。FIG. 1 is a sectional view of a multi-layer substrate showing one embodiment of the present invention. For the substrate 1 having high thermal conductivity and low expansion, the inter-plane connection hole 4 corresponding to the electronic circuit pattern
Are opened in advance, the insulator layer 2 and the conductor layer 3 are laminated on both sides of the substrate 1, and the insulator layer 2 and / or the conductor layer 3 are etched to form a predetermined electronic circuit pattern. A conductor is filled in the inter-plane connection hole 4 which needs to be connected to the conductor layer 3, and the inter-plane connection hole 4 for which connection is unnecessary is formed by a resist material 5.
Block with.
【０００９】[0009]
【発明の実施の形態】本発明の基板は、導電性物質で構
成することができ、具体的には、Ｔｉ系合金、Ｆｅ−Ｎ
ｉ系合金、Ｔｉ−Ｎｉ系合金、及び、Ａｌ−Ｎから選択
される合金で作製することができる。なお、本発明の基
板は上記の金属材料を用いた複合材を用いることも可能
である。BEST MODE FOR CARRYING OUT THE INVENTION The substrate of the present invention can be made of a conductive material, specifically, a Ti-based alloy, Fe-N
It can be made of an alloy selected from an i-based alloy, a Ti-Ni-based alloy, and Al-N. Note that a composite material using the above metal material can be used for the substrate of the present invention.
【００１０】これらの基板材料を用いることにより、下
記の特性を確保することが可能になった。 (i) 熱伝導性に優れているため、電子回路からの発熱を
効率的に逃がすことができ、多層基板の信頼性を向上さ
せることができた。 (ii)基板の強度が一般の金属材料と同等レベルであるた
め、優れた耐振性を得ることができた。By using these substrate materials, the following characteristics can be secured. (i) Because of its excellent thermal conductivity, heat from the electronic circuit can be efficiently released, and the reliability of the multilayer substrate can be improved. (ii) Since the strength of the substrate is equivalent to that of a general metal material, excellent vibration resistance can be obtained.
【００１１】(iii) これらの基板材料の熱膨張係数が、
ベアチップ材料の熱膨張係数に近いため、ベアチップの
実装信頼性が高く、─５５〜＋１５０℃で２００回の温
度サイクル試験にも十分に耐えることが確認された。 (iv)これらの基板材料を用いることにより、寸法誤差及
びソリを小さく抑えることが可能になり、±０．０５ｍ
ｍ以下の精度で基板を作製できるため、大型基板の製造
が可能になった。(Iii) The thermal expansion coefficient of these substrate materials is
Since the coefficient of thermal expansion is close to that of the bare chip material, it was confirmed that the mounting reliability of the bare chip was high and that it could sufficiently withstand a temperature cycle test of 200 times at # 55 to + 150 ° C. (iv) By using these substrate materials, dimensional errors and warpage can be suppressed to be small, ± 0.05 m
Since a substrate can be manufactured with an accuracy of less than m, a large substrate can be manufactured.
【００１２】(v) 基板材料として金属材料を用いること
ができるので、基板を電源グランドとして使用すること
により、高周波信号に対する耐ノイズ性が向上した。特
に、５ＧＨｚのスイッチング評価試験において、優れた
耐クロストーク性を有することが確認された。 (vi)基板の両面に電子回路を一体的に形成することがで
き、片側基板に比べて約２倍の部品高密度実装が可能に
なった。(V) Since a metal material can be used as the substrate material, the use of the substrate as a power supply ground improves noise resistance against high-frequency signals. In particular, in a switching evaluation test at 5 GHz, it was confirmed that it had excellent crosstalk resistance. (vi) Electronic circuits can be integrally formed on both surfaces of the substrate, and component high-density mounting about twice as large as that of a single-sided substrate has become possible.
【００１３】本発明の絶縁体層及び導体層は、ＣＶＤ法
（Chemical vapour deposition) やＰＶＤ法（Physical
vapour deposition) 等により積層して形成される。そ
して、絶縁体層及び導体層は、化学的エッチングや機械
加工で必要な部分のみを残して除去し、電子回路を形成
することができる。The insulator layer and the conductor layer of the present invention can be formed by CVD (Chemical vapor deposition) or PVD (Physical vapor deposition).
It is formed by laminating by vapor deposition or the like. Then, the insulator layer and the conductor layer are removed by chemical etching or machining, leaving only necessary portions, whereby an electronic circuit can be formed.
【００１４】ここで、絶縁体層を構成する絶縁材料とし
ては、Ａｌ2 Ｏ3 、ＳｉＯ2 、ＡｌＮ、ＢｅＯ、Ｓｉ
Ｃ、ＣａＯ、Ｎａ2 Ｏ、ＭｇＯ等を用いることができ
る。前記の絶縁体層の厚みは、１〜１０μｍの範囲が適
当である。また、導体層を構成する導電性材料として
は、Ａｌ、Ｃｕ、Ａｕ、Ａｇ、Ｎｉ、Ｃｒ、Ｐｔ等を用
いることができる。前記の導体層の厚みは、１〜１０μ
ｍの範囲が適当である。Here, as the insulating material constituting the insulator layer, Al 2 O 3 , SiO 2 , AlN, BeO, Si
C, CaO, Na 2 O, MgO or the like can be used. The thickness of the insulator layer is suitably in the range of 1 to 10 μm. Further, as a conductive material forming the conductor layer, Al, Cu, Au, Ag, Ni, Cr, Pt, or the like can be used. The thickness of the conductor layer is 1 to 10 μm.
The range of m is appropriate.
【００１５】さらに、電子回路パターンに対応したベア
チップ材料を蒸着して回路を形成することができる。ベ
アチップ材料として、Ｐｄ、Ｐｔ、Ｎｉ、Ｚｎ等の抵抗
値の大きな材料や、Ａｌ2 Ｏ3 、ＳｉＯ、ＳｉＯ2 、Ｂ
ｅＯ、ＭｇＣ、ＡｌＮ等の誘電率の高い材料を用いるこ
とができる。Furthermore, a circuit can be formed by depositing a bare chip material corresponding to the electronic circuit pattern. As a bare chip material, a material having a large resistance value such as Pd, Pt, Ni, Zn, or the like, or Al 2 O 3 , SiO, SiO 2 , B
A material having a high dielectric constant such as eO, MgC, or AlN can be used.
【００１６】本発明は、基板の両面に絶縁体層及び導体
層を蒸着して電子回路を形成するが、電子回路パターン
に対応する位置の基板に予め穴を開け、絶縁体層及び導
体層を積層するときに前記穴に導体材料を充填すること
により、基板を貫いて導体層を相互に接続して基板の両
面の電子回路を一体的に機能するように形成する。前記
の穴は、直径０．３〜２．０ｍｍの範囲が適当である。According to the present invention, an electronic circuit is formed by depositing an insulator layer and a conductor layer on both surfaces of a substrate. A hole is formed in the substrate at a position corresponding to the electronic circuit pattern, and the insulator layer and the conductor layer are formed. By filling the holes with a conductive material when laminating, the conductive layers are interconnected through the substrate to form electronic circuits on both sides of the substrate integrally. The hole preferably has a diameter of 0.3 to 2.0 mm.
【００１７】また、本発明では、絶縁体層と導体層の密
着性を向上させ、マイグレーションを防止するために、
両者の間に２０００オングストローム程度の薄い金属
層、具体的には、Ｃｒ、Ｎｉ等の層を介在させることが
好ましい。In the present invention, in order to improve the adhesion between the insulator layer and the conductor layer and prevent migration,
It is preferable to interpose a thin metal layer of about 2000 angstroms between them, specifically, a layer of Cr, Ni or the like.
【００１８】[0018]
【実施例】〔実施例１〕厚さ１ｍｍでサイズ１００×１
００ｍｍのＴｉ系合金、Ｆｅ−Ｎｉ系合金、Ａｌ−Ｎ等
の高熱伝導性かつ低熱膨張性の基板を用い、予め直径
０．３〜２．０ｍｍの穴を機械加工で開け、基板表面及
び穴の周囲を研磨加工して角をなくした。次に、真空度
１０-7〜１０-6Ｔｏｒｒの下で基板を２００±３０℃に
加熱して、蒸着速度３〜２０オングストローム／ｓｅｃ
で上記基板表面に厚さ１〜１０μｍのＡｌ2 Ｏ3 絶縁体
層を蒸着する。絶縁体層の成膜は、絶縁耐電圧に応じて
２〜５回に分割して行うこともできる。例えば、５００
ＶＤＣ−１０9 Ω以上のときには３分割で膜厚を各１．
０μｍづつ成膜できる。[Embodiment 1] 1 mm thick and 100 × 1 size
Using a substrate of high thermal conductivity and low thermal expansion such as 00 mm of a Ti-based alloy, Fe-Ni-based alloy, or Al-N, a hole having a diameter of 0.3 to 2.0 mm is previously formed by machining, and the substrate surface and the hole are formed. The corners were eliminated by polishing the area around. Next, the substrate is heated to 200 ± 30 ° C. under a degree of vacuum of 10 −7 to 10 −6 Torr, and a deposition rate of 3 to 20 Å / sec.
Then, an Al 2 O 3 insulator layer having a thickness of 1 to 10 μm is deposited on the surface of the substrate. The formation of the insulator layer can be performed in 2 to 5 times depending on the withstand voltage. For example, 500
When the voltage is equal to or higher than VDC-10 9 Ω, the film thickness is set to 1.
Films can be formed in 0 μm increments.
【００１９】次に、密着性を確保するために、上記基板
両面に厚さ２０００オングストロームのＣｒ薄膜を蒸着
し、その上に厚さ３μｍのＡｕ導体層を蒸着し、さらに
厚さ２０００オングストロームのＣｒ薄膜を蒸着する。
上記の薄膜は、密着性の向上、マイグレーションの防
止、Ａｌ2 Ｏ3 絶縁体層のエッチング信頼性の向上に大
きな役割をする。Next, in order to secure adhesion, a Cr thin film having a thickness of 2000 Å is deposited on both surfaces of the substrate, an Au conductor layer having a thickness of 3 μm is deposited thereon, and a Cr thin film having a thickness of 2000 Å is further formed. Deposit a thin film.
The thin film plays a major role in improving the adhesion, preventing migration, and improving the etching reliability of the Al 2 O 3 insulator layer.
【００２０】上記のＣｒ薄膜、Ａｕ導体層及びＣｒ薄膜
を形成した後、これらを所定のパターンに化学的にエッ
チングして電子回路を形成する。このエッチングには、
濃硫酸と濃硝酸の混合液を用いて常温で行う。上記のＣ
ｒ薄膜は、Ｎｉ薄膜に変更することも可能である。After the above-mentioned Cr thin film, Au conductor layer and Cr thin film are formed, these are chemically etched into a predetermined pattern to form an electronic circuit. In this etching,
This is performed at room temperature using a mixture of concentrated sulfuric acid and concentrated nitric acid. C above
The r thin film can be changed to a Ni thin film.
【００２１】なお、必要に応じて、上記Ｃｒ薄膜の上
に、上記と同様にＡｌ2 Ｏ3 絶縁体層、Ｃｒ薄膜、Ａｕ
導体層及びＣｒ薄膜を蒸着してさらなる多層化した後、
Ｃｒ薄膜、Ａｕ導体層及びＣｒ薄膜をエッチングして電
子回路を形成することも可能である。このような積層を
さらに繰り返すこも可能である。If necessary, an Al 2 O 3 insulator layer, a Cr thin film, Au
After depositing a conductor layer and a Cr thin film for further multilayering,
It is also possible to form an electronic circuit by etching the Cr thin film, the Au conductor layer and the Cr thin film. Such lamination can be further repeated.
【００２２】また、上記のＡｌ2 Ｏ3 絶縁体層に直径
０．３〜１．０μｍのビアホールを開け、必要なビアホ
ールにＡｕ導体を充填し、不要なビアホールはレジスト
材でシールをして該絶縁体層の上下の電子回路を一体的
に接続する。Ａｌ2 Ｏ3 絶縁体層のビアホールは、リン
酸・硝酸混合液を用いて７５℃程度でエッチングして形
成する。このエッチングによれば、下層のＡｕ導体層上
で確実に止めることができる。A via hole having a diameter of 0.3 to 1.0 μm is formed in the Al 2 O 3 insulator layer, a necessary via hole is filled with an Au conductor, and an unnecessary via hole is sealed with a resist material. Electronic circuits above and below the insulator layer are integrally connected. The via holes in the Al 2 O 3 insulator layer are formed by etching at about 75 ° C. using a mixed solution of phosphoric acid and nitric acid. According to this etching, it can be reliably stopped on the lower Au conductor layer.
【００２３】[0023]
【発明の効果】本発明は、上記の構成を採用することに
より、基板の放熱を確実にし、優れた耐振性を有し、電
子回路の高密度化、小型化を可能にした多層基板の提供
が可能になった。According to the present invention, there is provided a multi-layer substrate which employs the above-described structure, ensures heat radiation of the substrate, has excellent vibration resistance, and enables high density and miniaturization of electronic circuits. Is now possible.
【図１】本発明の１具体例である多層基板の断面図であ
る。FIG. 1 is a cross-sectional view of a multilayer substrate according to one embodiment of the present invention.
Claims (3)
両面に、絶縁体層及び導体層を必要な層数だけ繰り返し
て積層し、絶縁体層及び／又は導体層をエッチングして
所定の電子回路パターンを形成してなることを特徴とす
る電子回路用多層基板。An insulator layer and a conductor layer are repeatedly laminated on both sides of a substrate having a high thermal conductivity and a low expansion property by a required number of layers, and the insulator layer and / or the conductor layer are etched to a predetermined number. An electronic circuit multilayer substrate formed by forming an electronic circuit pattern.
板に予め穴を開け、前記絶縁体層及び前記導体層を積層
し、前記穴に導体を充填することにより、前記基板の両
面の前記導体層を相互に接続して電子回路を形成してな
ることを特徴とする請求項１記載の電子回路用多層基
板。2. A method according to claim 1, wherein a hole is formed in the substrate corresponding to the electronic circuit pattern in advance, the insulator layer and the conductor layer are laminated, and the hole is filled with a conductor. 2. The multilayer substrate for an electronic circuit according to claim 1, wherein the electronic circuit is formed by connecting the components to each other.
者の密着性を確保するための薄い金属層を設けてなるこ
とを特徴とする請求項１又は２記載の電子回路用多層基
板。3. The multilayer for electronic circuits according to claim 1, wherein a thin metal layer is provided between the insulator layer and the conductor layer to secure adhesion between the two. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715698A JPH11330292A (en) | 1998-05-11 | 1998-05-11 | Multilayer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715698A JPH11330292A (en) | 1998-05-11 | 1998-05-11 | Multilayer substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11330292A true JPH11330292A (en) | 1999-11-30 |
Family
ID=14953030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12715698A Pending JPH11330292A (en) | 1998-05-11 | 1998-05-11 | Multilayer substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11330292A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100843368B1 (en) | 2007-03-02 | 2008-07-03 | 삼성전기주식회사 | Fabricating method of multi layer printed circuit board |
| US20110109332A1 (en) * | 2009-11-09 | 2011-05-12 | Murata Manufacturing Co., Ltd. | Electrical characteristic measuring substrate |
-
1998
- 1998-05-11 JP JP12715698A patent/JPH11330292A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100843368B1 (en) | 2007-03-02 | 2008-07-03 | 삼성전기주식회사 | Fabricating method of multi layer printed circuit board |
| US20110109332A1 (en) * | 2009-11-09 | 2011-05-12 | Murata Manufacturing Co., Ltd. | Electrical characteristic measuring substrate |
| US8698514B2 (en) * | 2009-11-09 | 2014-04-15 | Murata Manufacturing Co., Ltd. | Electrical characteristic measuring substrate |
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