JPS58103156A - Substrate for semiconductor device - Google Patents

Substrate for semiconductor device

Info

Publication number
JPS58103156A
JPS58103156A JP20315981A JP20315981A JPS58103156A JP S58103156 A JPS58103156 A JP S58103156A JP 20315981 A JP20315981 A JP 20315981A JP 20315981 A JP20315981 A JP 20315981A JP S58103156 A JPS58103156 A JP S58103156A
Authority
JP
Japan
Prior art keywords
substrate
mounting
coated
thermal conductivity
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20315981A
Other languages
Japanese (ja)
Other versions
JPS6027188B2 (en
Inventor
Akira Matsumura
松村 昭
Nobuo Ogasa
小笠 伸夫
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP20315981A priority Critical patent/JPS6027188B2/en
Publication of JPS58103156A publication Critical patent/JPS58103156A/en
Publication of JPS6027188B2 publication Critical patent/JPS6027188B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Abstract

PURPOSE:To obtain the substrate for mounting of the semiconductor element having superior heat radiation by a method wherein a film consisting of an organic matter having the electrically insulating property and moreover having comparatively favorable thermal conductivity is coated as a thin layer on the surface of a tape of metal, alloy or composite thereof having favorable thermal conductivity. CONSTITUTION:The metal substrate 1 for mounting of the Si semiconductor element 6 and coated with the SiC thin film 4 is manufactured according to the plasma CVD method, and copper of 1.0mm. thickness and containing Zr is used for the metal substrate 1. The plasma CVD method is performed using a capacitive coupling type glow discharge device and mixed gas of 1X10<-2> Torr of SiH4 and CH4, and by heating the substrate at 500 deg.C. Accordingly the substrate 3 for mounting of the semiconductor coated with the SiC thin film 4 of 3mum thickness having favorable adhesion, having the dielectric strength characteristic of 3MV/ cm or more, having the coefficient of thermal expansion approximated to the Si element to be mounted and having superior heat radiation is obtained.

Description

【発明の詳細な説明】 ゛一本発明は、集積回路装置の素子塔載基板材に関する
ものであり、半導体素子に発生する熱を特に効率より放
熱し得ると共に、電気絶縁性を有する半導体装置用基板
材料を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate material for mounting an element on an integrated circuit device, which is particularly capable of dissipating heat generated in a semiconductor element with high efficiency, and having an electrically insulating property. It provides substrate materials.

集積回路のうち、高信頼性を必要とするものには、低融
点ガラス、セラミックパッケージや多層セラミックパッ
ケージなどのパンケージ法が従来から用いられている。
BACKGROUND OF THE INVENTION For integrated circuits that require high reliability, pancage methods such as low-melting glass, ceramic packages, and multilayer ceramic packages have traditionally been used.

この場合半導体素子はセラミック基板の上に接着の為の
メタルライジング層やメッキ層を介して半導体が塔載さ
れるのが一般的である。この基板は、それ自体気密封止
機能を果すパッケージ材料の一部としてのみですく、電
気絶縁性や半導体素子との熱膨張係数のミスマツチが小
さいなどの特性が要求されている。このため従来はAj
1208.Be0.2Mg0.SiO,等の焼結セラミ
ック材料が広く用いられている。
In this case, the semiconductor element is generally mounted on a ceramic substrate via a metal rising layer or a plating layer for adhesion. This substrate itself can only be used as a part of the package material that performs a hermetic sealing function, and is required to have properties such as electrical insulation and a small mismatch in thermal expansion coefficient with the semiconductor element. For this reason, conventionally Aj
1208. Be0.2Mg0. Sintered ceramic materials such as SiO, etc. are widely used.

しかし乍ら、近年集積回路素子の高密度化及び大型化が
進行し、高密度化により半導体素子からの発熱量の増大
を招き基板材料に対する放熱性の要求がますます大きく
なり′つつある。この為、レジンモールドタイプのI’
Cに用いられるリードフレームにはその素材がNi合金
からCu合金の変換しつつある。低融点ガラスセラミッ
クパッケージや多層セラミックパッケージの集積回路に
ついても同様に放熱性の要求が強いが、Aj1208 
 ヤ2Mg0 Sin、では本質的に熱伝導率が悪く、
この要求に答え難い。わずかに良熱導性材であるBeO
があるが、これは高価である上に毒性を有するという難
点がある。又最も多用されているA608はその成型、
焼結時に混入するUより発生するα線による半導体素子
への照射効果によって起る集積回路の誤動作がこの高性
能、高信頼性化の要求の強まる中で、大きな問題になり
つつある。
However, in recent years, integrated circuit elements have become denser and larger, and the higher density has led to an increase in the amount of heat generated from the semiconductor elements, and the requirements for heat dissipation properties of substrate materials are becoming greater. For this reason, the resin mold type I'
The material for the lead frame used in C is changing from Ni alloy to Cu alloy. There is also a strong demand for heat dissipation for integrated circuits in low-melting-point glass-ceramic packages and multilayer ceramic packages, but Aj1208
Y2Mg0Sin has inherently poor thermal conductivity,
It is difficult to answer this request. BeO, a material with slightly good thermal conductivity
However, this method has the drawbacks of being expensive and toxic. Also, the most commonly used A608 is its molding,
Malfunctions of integrated circuits caused by the irradiation effect on semiconductor elements by alpha rays generated from U mixed during sintering are becoming a major problem as demands for higher performance and reliability become stronger.

本発明は、かかる欠点を解消し、従来のセラミック基板
に梼る放熱性良好な半導体素子搭載用基板材料を提供せ
んとするものである。
The present invention aims to eliminate such drawbacks and provide a substrate material for mounting semiconductor elements that has better heat dissipation properties than conventional ceramic substrates.

すなわち、本発明の半導体素子搭載用基板材料は、ベー
スメタルとして熱伝導性良好なる金属、合金、焼結体又
は、これらの複合テープを用い、この表面に電気絶縁性
を有し、且つ比較的熱伝導性が良好な無機物質の皮膜を
薄層被覆したものである。ここで言うベースメタルとし
ては、Ni。
That is, the substrate material for mounting a semiconductor element of the present invention uses a metal, alloy, sintered body, or a composite tape of these as a base metal, has electrical insulation properties on the surface, and has a relatively low heat conductivity. It is coated with a thin layer of inorganic material that has good thermal conductivity. The base metal mentioned here is Ni.

Cu * AIノ他s近年、ICリードフレーム用に開
発された各種、高電気伝導性Cu合金などの薄板テープ
並びに、所要の熱伝導率と機械的性質を任意に設定でき
るように、銅クラツドステンレス鋼クラツド銅などの複
合板を用いることが、特に有効である。又この表面に被
覆される材料としてはダイヤモンドの他BN、AJ O
AjN、SiC,Si、N4゜  8− Y、08# 2Mgo e S iO,等のセラミック
材が有効であり、これらは回路基板の要求特性に応じて
適宜材料及びその組合せを選択し、また膜厚も任意に制
御することができる。
In recent years, various types of thin plate tapes such as highly electrically conductive Cu alloys have been developed for IC lead frames, as well as copper clad tapes that allow the required thermal conductivity and mechanical properties to be set arbitrarily. It is particularly effective to use composite plates such as stainless steel clad copper. In addition to diamond, materials coated on this surface include BN, AJO, etc.
Ceramic materials such as AjN, SiC, Si, N4°8-Y, 08#2Mgoe SiO, etc. are effective, and these materials and their combinations should be selected appropriately according to the required characteristics of the circuit board, and the film thickness can also be controlled arbitrarily.

このような七ラミック被覆金属と言う複合型基板によっ
て、半導体素子の差異や半導体装置としての要求特性と
要求価格に応じて、材質の組合せ構成比を選択すること
により、今後ますます増大する高密度かつ大型化する半
導体素子に対応できる。又Si集積回路に加えて今後実
用化が進むと考えられるGaAs集積回路のパッケージ
用材料としても活用できる集積回路装置の半導体素子塔
載用基板材を提供することが可能である。
By using such a composite substrate called heptadramic-coated metal, the composition ratio of material combinations can be selected according to the differences in semiconductor elements and the required characteristics and price of semiconductor devices. In addition, it can accommodate semiconductor devices that are becoming larger. In addition to Si integrated circuits, it is also possible to provide a substrate material for mounting semiconductor elements in integrated circuit devices that can be used as a packaging material for GaAs integrated circuits, which are expected to be put into practical use in the future.

タイヤモンド又前述のはセラミックスを被覆スる方法と
しては、物理的蒸着(PVD)、化学的蒸着(CVD)
などの気相メッキ法を用いることが好ましい。
The methods of coating ceramics mentioned above include physical vapor deposition (PVD) and chemical vapor deposition (CVD).
It is preferable to use a vapor phase plating method such as

本発明において、ベースメタルの熱伝導率を0、BOC
al/cm、sec”0以上と限定しり(i’) ハ、
従来用いられているAj 、0812Mg0.S io
gなどの焼粘土ラミックを用いた基板材料では得ること
ができない。高鵬伝導性を得る為で、今後ますますIC
における放熱性への要求が増大するのに対処する為であ
る。湖、本発明において、従来、半導体素子搭載用基板
の要求特性の1つであった熱膨張特性を、ベースメタル
の選定において特に考慮しなかったのは、近年、ダイボ
ンディング技術や、封止技術の発達によりIC実装工程
での低温処理技術が著しく進歩し、大型の半導体素子を
用いる場合を除いて、大きな問題点とはなっていないこ
とによる。伺、熱膨張特性が必要な場合には、MO,W
In the present invention, the thermal conductivity of the base metal is 0, BOC
al/cm, sec" limited to 0 or more (i') Ha,
Conventionally used Aj, 0812Mg0. S io
This cannot be obtained with a substrate material using baked clay lamic such as G. In order to obtain high conductivity, more and more ICs will be used in the future.
This is to cope with the increasing demand for heat dissipation in However, in the present invention, thermal expansion characteristics, which had traditionally been one of the required characteristics of a substrate for mounting semiconductor elements, were not particularly taken into account when selecting the base metal.In recent years, die bonding technology and sealing technology This is because low-temperature processing technology in the IC mounting process has significantly advanced due to the development of technology, and this has not become a major problem except when large semiconductor elements are used. However, if thermal expansion characteristics are required, MO, W
.

や、銅クラツドコバールクラツド銅などの複合板・をベ
ースメタルとして用いることにより、要求特性を満足す
ることができる。
The required characteristics can be satisfied by using a composite plate such as copper-clad or Kovar-clad copper as the base metal.

又表面被覆の厚みを0.1〜10μm と限定したのは
、これ以下では所要の電気絶縁性を得ることができず、
これ以上になると被覆の為のコストが著しく大きくなり
、経済性の面で実用性が乏しいためである。
Moreover, the reason why the thickness of the surface coating was limited to 0.1 to 10 μm is that the required electrical insulation cannot be obtained with less than this.
This is because if the amount exceeds this value, the cost for coating becomes extremely high, making it impractical from an economical point of view.

第1図は本発明の基板を用いて半導体素子を塔載した半
導体装置の断面図であり、1が素子の熱伝導率が良好な
る金属板又は複合金属板であり、2がその表面に被覆さ
れた絶縁被覆層で、基板3を形成する。4はメタルライ
ジング層、5はAuメッキ層で、これを介して半導体素
子6が塔載される。
FIG. 1 is a cross-sectional view of a semiconductor device on which a semiconductor element is mounted using the substrate of the present invention, in which 1 is a metal plate or composite metal plate with good thermal conductivity of the element, and 2 is a coating on the surface. A substrate 3 is formed using the insulating coating layer. 4 is a metal rising layer, 5 is an Au plating layer, and a semiconductor element 6 is mounted thereon.

以下実施例によって詳しく説明する。This will be explained in detail below using examples.

実施例1 Si半導体素子を塔載するためのSiC薄膜を被覆した
金属基板をプラズマCVD 法で作製した。
Example 1 A metal substrate coated with a SiC thin film for mounting a Si semiconductor element was fabricated by plasma CVD.

金属基板には厚さ1.0■のZr含有銅を用いた。Zr-containing copper having a thickness of 1.0 cm was used for the metal substrate.

プラズマCVD は容量結合型グロー放電装置を用い1
xlO”TorrのSiH,とCH,の混合ガスを用い
基板は500℃ に加熱して行った。8 MV/ffi
以上の絶縁耐圧特性を有する8μmのSiC薄膜を密着
性良く被覆した熱膨張係数が搭載するSi素子と近似し
た熱放散性に優れた半導体搭載用基板を得ることが出来
た。
Plasma CVD uses a capacitively coupled glow discharge device.
The substrate was heated to 500°C using a mixed gas of SiH and CH at xlO" Torr. 8 MV/ffi
It was possible to obtain a substrate for mounting a semiconductor, which was coated with a SiC thin film of 8 μm having the above dielectric strength characteristics with good adhesion and had excellent heat dissipation and a coefficient of thermal expansion similar to that of the Si element on which it is mounted.

実施例2 Si半導体素子を塔載するためのAl2O8薄膜を被覆
した金属基板をイオンブレーティング法で作製した。
Example 2 A metal substrate coated with an Al2O8 thin film on which a Si semiconductor element was mounted was fabricated by an ion blasting method.

金属のベースメタルとしては、厚さ0.511m の無
酸素純銅板を用い、イオンブレーティングは、次の方法
により実施した。
An oxygen-free pure copper plate having a thickness of 0.511 m was used as the base metal, and ion blating was carried out by the following method.

原料にはA、l、03 焼結体を用い、電子ビーム加熱
ニヨリ蒸発させた。酸素圧4X10 ”rorrms周
波(13,56MHz) 100〜20 owを印加し
て蒸発物質の一部をイオン化し、基板を200℃ に加
熱してAlz Oa  を厚さ2.0μm被覆した。8
MV/備以上の絶縁耐圧特性を有する透明な絶縁体薄膜
を密着性良く熱放散性に優れた半導体素子搭載用基板を
得ることが出来た。
A, l, 03 sintered body was used as the raw material and evaporated by electron beam heating. A portion of the evaporated material was ionized by applying an oxygen pressure of 4×10”rorrms frequency (13,56 MHz) of 100 to 20 ow, and the substrate was heated to 200° C. to coat AlzOa to a thickness of 2.0 μm.8
It was possible to obtain a substrate for mounting a semiconductor element, which has a transparent insulating thin film having dielectric strength characteristics of MV/VI or higher, has good adhesion, and has excellent heat dissipation properties.

以上、説明した如く、高熱伝導性のベースメタル上に、
ダイヤモンド、又は、セラミックスを薄層波することに
より、熱放散性に優れた半導体素子搭載用基板が得られ
た。これにより、集積回路の大型化、高密度化に充分対
応できるようになった。
As explained above, on a highly thermally conductive base metal,
By corrugating diamond or ceramic into a thin layer, a substrate for mounting a semiconductor element with excellent heat dissipation properties was obtained. This has made it possible to fully cope with the increasing size and density of integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による基板を用いた半導体装置の横穴的
断面図である。 に金属板、2:絶縁被覆層、3:基板、4:メタルライ
ジング層、5 : Au メッキ層、6:半導体素子。 片1図
FIG. 1 is a horizontal sectional view of a semiconductor device using a substrate according to the present invention. 2: insulating coating layer, 3: substrate, 4: metal rising layer, 5: Au plating layer, 6: semiconductor element. Piece 1

Claims (4)

【特許請求の範囲】[Claims] (1)熱伝導率が0.2 Ca I / cm、 se
e ’G以上である金属板、又は複合金属板の表面及び
側面に、PVD法又はCVD法によって被覆された電気
絶縁性の無機物質が0.1−10μm の厚みの薄層被
覆を有することを特徴とする半導体素子搭載用の半導体
装置用基板。
(1) Thermal conductivity is 0.2 Ca I/cm, se
The surface and side surfaces of a metal plate or a composite metal plate with an e'G or higher are coated with a thin layer of electrically insulating inorganic material with a thickness of 0.1-10 μm by PVD or CVD. A semiconductor device substrate for mounting semiconductor elements.
(2)半導体素子がSi 又はG a A sであるこ
とを特徴とする特許請求の範囲第(1)項記載の半導体
装置用基板。
(2) The substrate for a semiconductor device according to claim (1), wherein the semiconductor element is Si or GaAs.
(3)金属板又は複合金属板が、N r + Cu 、
 Aj +各種高熱伝導型Cu合金、銅フラッドステン
レス鋼クラッド銅、又はM。又はWを主体とする焼結体
であることを特徴とする特許請求の範囲第(1)項記載
の半導体装置用基板。
(3) The metal plate or composite metal plate has N r + Cu,
Aj + Various high thermal conductivity type Cu alloys, copper flooded stainless steel clad copper, or M. The substrate for a semiconductor device according to claim (1), wherein the substrate is a sintered body mainly composed of W.
(4)被覆層がBN 、Aj208.AjIN、SiC
,8i8N、 。 YsOs 、2Mg0.S+02.ダイヤモンドのいず
れかであることを特徴とする特許請求の範囲第(1)項
記載の半導体装置用基板。
(4) The coating layer is BN, Aj208. AjIN, SiC
,8i8N, . YsOs, 2Mg0. S+02. The substrate for a semiconductor device according to claim (1), characterized in that the substrate is made of diamond.
JP20315981A 1981-12-15 1981-12-15 Substrate for mounting semiconductor elements Expired JPS6027188B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20315981A JPS6027188B2 (en) 1981-12-15 1981-12-15 Substrate for mounting semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20315981A JPS6027188B2 (en) 1981-12-15 1981-12-15 Substrate for mounting semiconductor elements

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP10728886A Division JPS6224647A (en) 1986-05-10 1986-05-10 Substrate for mounting semiconductor element
JP10728986A Division JPS6224648A (en) 1986-05-10 1986-05-10 Substrate for mounting semiconductor element
JP10729086A Division JPS61292345A (en) 1986-05-10 1986-05-10 Substrate for mounting semiconductor element

Publications (2)

Publication Number Publication Date
JPS58103156A true JPS58103156A (en) 1983-06-20
JPS6027188B2 JPS6027188B2 (en) 1985-06-27

Family

ID=16469407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20315981A Expired JPS6027188B2 (en) 1981-12-15 1981-12-15 Substrate for mounting semiconductor elements

Country Status (1)

Country Link
JP (1) JPS6027188B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62108551A (en) * 1985-11-06 1987-05-19 Kanegafuchi Chem Ind Co Ltd High heat-conductive insulating substrate and manufacture thereof
JPS62154650A (en) * 1985-12-26 1987-07-09 Kanegafuchi Chem Ind Co Ltd Insulating substrate having high thermal conductivity and manufacture thereof
JPS62297299A (en) * 1986-06-16 1987-12-24 Kobe Steel Ltd Diamond radiator
JPS6489448A (en) * 1987-06-23 1989-04-03 Texas Instruments Inc High-performance heat sink and mounting member of semiconductor products, and manufacture thereof
JPH0513616A (en) * 1991-10-03 1993-01-22 Kanegafuchi Chem Ind Co Ltd High thermal conductive insulating substrate and its manufacture
JP2014158025A (en) * 2013-02-18 2014-08-28 Triquint Semiconductor Inc Package for high-power semiconductor devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62108551A (en) * 1985-11-06 1987-05-19 Kanegafuchi Chem Ind Co Ltd High heat-conductive insulating substrate and manufacture thereof
JPS62154650A (en) * 1985-12-26 1987-07-09 Kanegafuchi Chem Ind Co Ltd Insulating substrate having high thermal conductivity and manufacture thereof
JPS62297299A (en) * 1986-06-16 1987-12-24 Kobe Steel Ltd Diamond radiator
JPS6489448A (en) * 1987-06-23 1989-04-03 Texas Instruments Inc High-performance heat sink and mounting member of semiconductor products, and manufacture thereof
JPH0513616A (en) * 1991-10-03 1993-01-22 Kanegafuchi Chem Ind Co Ltd High thermal conductive insulating substrate and its manufacture
JP2014158025A (en) * 2013-02-18 2014-08-28 Triquint Semiconductor Inc Package for high-power semiconductor devices

Also Published As

Publication number Publication date
JPS6027188B2 (en) 1985-06-27

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