JPH0377660B2 - - Google Patents

Info

Publication number
JPH0377660B2
JPH0377660B2 JP58110768A JP11076883A JPH0377660B2 JP H0377660 B2 JPH0377660 B2 JP H0377660B2 JP 58110768 A JP58110768 A JP 58110768A JP 11076883 A JP11076883 A JP 11076883A JP H0377660 B2 JPH0377660 B2 JP H0377660B2
Authority
JP
Japan
Prior art keywords
layer
metal
oxide layer
oxide
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58110768A
Other languages
English (en)
Japanese (ja)
Other versions
JPS595629A (ja
Inventor
Kyanderaria Jon
Esu Haideingaa Kaato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23544996&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH0377660(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPS595629A publication Critical patent/JPS595629A/ja
Publication of JPH0377660B2 publication Critical patent/JPH0377660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Laminated Bodies (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Weting (AREA)
JP58110768A 1982-06-21 1983-06-20 二重層表面安定化方法 Granted JPS595629A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US391047 1982-06-21
US06/391,047 US4446194A (en) 1982-06-21 1982-06-21 Dual layer passivation

Publications (2)

Publication Number Publication Date
JPS595629A JPS595629A (ja) 1984-01-12
JPH0377660B2 true JPH0377660B2 (enExample) 1991-12-11

Family

ID=23544996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58110768A Granted JPS595629A (ja) 1982-06-21 1983-06-20 二重層表面安定化方法

Country Status (2)

Country Link
US (1) US4446194A (enExample)
JP (1) JPS595629A (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985373A (en) * 1982-04-23 1991-01-15 At&T Bell Laboratories Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures
JPS6196751A (ja) * 1984-10-17 1986-05-15 Nec Corp 半導体装置
US4972251A (en) * 1985-08-14 1990-11-20 Fairchild Camera And Instrument Corp. Multilayer glass passivation structure and method for forming the same
US4874716A (en) * 1986-04-01 1989-10-17 Texas Instrument Incorporated Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface
GB2202085B (en) * 1987-01-27 1990-02-14 Ricoh Kk Amorphous silicon photosensor
US5010024A (en) * 1987-03-04 1991-04-23 Advanced Micro Devices, Inc. Passivation for integrated circuit structures
JPH084109B2 (ja) * 1987-08-18 1996-01-17 富士通株式会社 半導体装置およびその製造方法
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
US4966870A (en) * 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
US5157001A (en) * 1989-09-18 1992-10-20 Matsushita Electric Industrial Co., Ltd. Method of dicing semiconductor wafer along protective film formed on scribe lines
TW214599B (enExample) * 1990-10-15 1993-10-11 Seiko Epson Corp
DE4136987A1 (de) * 1991-11-11 1993-05-13 Leybold Ag Verfahren zur oberflaechenpassivierung von sensoren
JPH05243402A (ja) * 1992-03-03 1993-09-21 Nec Corp 半導体装置の製造方法
US5516729A (en) * 1994-06-03 1996-05-14 Advanced Micro Devices, Inc. Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
US6300253B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6323139B1 (en) 1995-12-04 2001-11-27 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials
US5926739A (en) 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US5960306A (en) * 1995-12-15 1999-09-28 Motorola, Inc. Process for forming a semiconductor device
US5750419A (en) * 1997-02-24 1998-05-12 Motorola, Inc. Process for forming a semiconductor device having a ferroelectric capacitor
US6025263A (en) * 1997-07-15 2000-02-15 Nanya Technology Corporation Underlayer process for high O3 /TEOS interlayer dielectric deposition
JPH1138192A (ja) * 1997-07-17 1999-02-12 Nikon Corp 多層膜反射鏡
US6635530B2 (en) * 1998-04-07 2003-10-21 Micron Technology, Inc. Methods of forming gated semiconductor assemblies
US6316372B1 (en) 1998-04-07 2001-11-13 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US5985771A (en) * 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6136688A (en) * 1999-10-20 2000-10-24 Vanguard International Semiconductor Corporation High stress oxide to eliminate BPSG/SiN cracking
SG114574A1 (en) * 2002-09-25 2005-09-28 Siltronic Singapore Pte Ltd Two layer lto backside seal for a wafer
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
US20090115060A1 (en) * 2007-11-01 2009-05-07 Infineon Technologies Ag Integrated circuit device and method
DE102009025977A1 (de) * 2009-06-16 2010-12-23 Q-Cells Se Solarzelle und Herstellungsverfahren einer Solarzelle

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560810A (en) * 1968-08-15 1971-02-02 Ibm Field effect transistor having passivated gate insulator
DE2452289A1 (de) * 1974-11-04 1976-05-06 Siemens Ag Halbleiterbauelement
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
US4091407A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
US4091406A (en) * 1976-11-01 1978-05-23 Rca Corporation Combination glass/low temperature deposited Siw Nx Hy O.sub.z
JPS5736834A (ja) * 1980-08-15 1982-02-27 Hitachi Ltd Handotaisochi

Also Published As

Publication number Publication date
US4446194A (en) 1984-05-01
JPS595629A (ja) 1984-01-12

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