JPH0357623B2 - - Google Patents

Info

Publication number
JPH0357623B2
JPH0357623B2 JP60214852A JP21485285A JPH0357623B2 JP H0357623 B2 JPH0357623 B2 JP H0357623B2 JP 60214852 A JP60214852 A JP 60214852A JP 21485285 A JP21485285 A JP 21485285A JP H0357623 B2 JPH0357623 B2 JP H0357623B2
Authority
JP
Japan
Prior art keywords
resin
resin sealing
sealing part
sealed
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60214852A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6276659A (ja
Inventor
Hiroshi Matsumoto
Takao Emoto
Toshihiro Kato
Shinjiro Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60214852A priority Critical patent/JPS6276659A/ja
Priority to EP86304725A priority patent/EP0206771B1/en
Priority to DE8686304725T priority patent/DE3684184D1/de
Priority to KR1019860006270A priority patent/KR900001668B1/ko
Publication of JPS6276659A publication Critical patent/JPS6276659A/ja
Priority to US07/334,771 priority patent/US4924351A/en
Publication of JPH0357623B2 publication Critical patent/JPH0357623B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP60214852A 1985-06-20 1985-09-30 樹脂封止型半導体装置 Granted JPS6276659A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP60214852A JPS6276659A (ja) 1985-09-30 1985-09-30 樹脂封止型半導体装置
EP86304725A EP0206771B1 (en) 1985-06-20 1986-06-19 Packaged semiconductor device
DE8686304725T DE3684184D1 (de) 1985-06-20 1986-06-19 Verkapselte halbleiteranordnung.
KR1019860006270A KR900001668B1 (ko) 1985-09-30 1986-07-30 수지봉합형 반도체장치
US07/334,771 US4924351A (en) 1985-06-20 1989-04-10 Recessed thermally conductive packaged semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60214852A JPS6276659A (ja) 1985-09-30 1985-09-30 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPS6276659A JPS6276659A (ja) 1987-04-08
JPH0357623B2 true JPH0357623B2 (enFirst) 1991-09-02

Family

ID=16662612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60214852A Granted JPS6276659A (ja) 1985-06-20 1985-09-30 樹脂封止型半導体装置

Country Status (2)

Country Link
JP (1) JPS6276659A (enFirst)
KR (1) KR900001668B1 (enFirst)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3035403B2 (ja) * 1992-03-09 2000-04-24 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
KR870003559A (ko) 1987-04-18
JPS6276659A (ja) 1987-04-08
KR900001668B1 (ko) 1990-03-17

Similar Documents

Publication Publication Date Title
JP2509607B2 (ja) 樹脂封止型半導体装置
US6894376B1 (en) Leadless microelectronic package and a method to maximize the die size in the package
US4712127A (en) High reliability metal and resin container for a semiconductor device
JP2959480B2 (ja) 半導体装置及びその製造方法
US6576491B1 (en) Methods for producing high reliability lead frame and packaging semiconductor die using such lead frame
KR900001984B1 (ko) 수지봉합형 반도체장치
JPH0357623B2 (enFirst)
JPH0254665B2 (enFirst)
JPS6223097Y2 (enFirst)
JPH11289031A (ja) 半導体装置及びその製造方法
JP3013810B2 (ja) 半導体装置の製造方法
JP2710207B2 (ja) 半導体装置およびその製造方法
JPH05267503A (ja) 半導体装置
JP2939094B2 (ja) 電力用半導体装置の製造方法
JPH04168753A (ja) 半導体装置
JPS5986251A (ja) 樹脂封止型半導体装置用リ−ドフレ−ム
JPH0415942A (ja) 半導体装置
JPS5918684Y2 (ja) 樹脂封止型半導体装置
KR100321149B1 (ko) 칩사이즈 패키지
KR20000026099A (ko) 칩크기 반도체 패키지와 그 제조방법
JP2814006B2 (ja) 電子部品搭載用基板
JPS635250Y2 (enFirst)
JPH02202042A (ja) 樹脂封止型半導体装置
JPS61177760A (ja) ピングリツドアレイ型半導体装置及びその製造方法
JP2000304638A (ja) センサチップの接合構造

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term