JPH0349485Y2 - - Google Patents
Info
- Publication number
- JPH0349485Y2 JPH0349485Y2 JP15708785U JP15708785U JPH0349485Y2 JP H0349485 Y2 JPH0349485 Y2 JP H0349485Y2 JP 15708785 U JP15708785 U JP 15708785U JP 15708785 U JP15708785 U JP 15708785U JP H0349485 Y2 JPH0349485 Y2 JP H0349485Y2
- Authority
- JP
- Japan
- Prior art keywords
- latch circuits
- latch
- circuit
- output
- nand gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007257 malfunction Effects 0.000 claims description 13
- 230000008054 signal transmission Effects 0.000 claims description 12
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Small-Scale Networks (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15708785U JPH0349485Y2 (en:Method) | 1985-10-16 | 1985-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15708785U JPH0349485Y2 (en:Method) | 1985-10-16 | 1985-10-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6266443U JPS6266443U (en:Method) | 1987-04-24 |
| JPH0349485Y2 true JPH0349485Y2 (en:Method) | 1991-10-22 |
Family
ID=31079310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15708785U Expired JPH0349485Y2 (en:Method) | 1985-10-16 | 1985-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0349485Y2 (en:Method) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313446A (ja) * | 1986-07-03 | 1988-01-20 | Fujitsu Ltd | デ−タ誤り訂正回路 |
| JP2562703B2 (ja) * | 1989-12-27 | 1996-12-11 | 株式会社小松製作所 | 直列制御装置のデータ入力制御装置 |
-
1985
- 1985-10-16 JP JP15708785U patent/JPH0349485Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6266443U (en:Method) | 1987-04-24 |
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