JPH0323021B2 - - Google Patents

Info

Publication number
JPH0323021B2
JPH0323021B2 JP59109209A JP10920984A JPH0323021B2 JP H0323021 B2 JPH0323021 B2 JP H0323021B2 JP 59109209 A JP59109209 A JP 59109209A JP 10920984 A JP10920984 A JP 10920984A JP H0323021 B2 JPH0323021 B2 JP H0323021B2
Authority
JP
Japan
Prior art keywords
signal
timing
polarity
converter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59109209A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60251740A (ja
Inventor
Yasutsune Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59109209A priority Critical patent/JPS60251740A/ja
Publication of JPS60251740A publication Critical patent/JPS60251740A/ja
Publication of JPH0323021B2 publication Critical patent/JPH0323021B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59109209A 1984-05-29 1984-05-29 タイミング同期回路 Granted JPS60251740A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59109209A JPS60251740A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59109209A JPS60251740A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Publications (2)

Publication Number Publication Date
JPS60251740A JPS60251740A (ja) 1985-12-12
JPH0323021B2 true JPH0323021B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-03-28

Family

ID=14504360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59109209A Granted JPS60251740A (ja) 1984-05-29 1984-05-29 タイミング同期回路

Country Status (1)

Country Link
JP (1) JPS60251740A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2543515B2 (ja) * 1987-03-04 1996-10-16 富士通株式会社 クロツク再生回路
SE469616B (sv) * 1991-12-23 1993-08-02 Ellemtel Utvecklings Ab Anordning foer foerskjutning av fasen hos en klocksignal samt saett och anordning foer taktaatervinning hos en digital datasignal

Also Published As

Publication number Publication date
JPS60251740A (ja) 1985-12-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees