JPH0323021B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a timing synchronization circuit, and more particularly to an improvement in a timing synchronization circuit that reproduces a timing signal for converting a demodulated signal into a predetermined digital signal from a band-limited baseband signal. (Prior Art) In a demodulator used in a digital carrier wave transmission system, a predetermined timing signal is generally required in order to convert a demodulated signal into a digital signal. Conventionally, as a means for reproducing this timing signal, a timing synchronization circuit as shown in FIG. 1 is used as an example. The timing synchronization circuit shown in Figure 1 is a two-phase
It is compatible with demodulators using the PSK (Phase Shift Keying) method, and includes a 1-bit A/D converter 1, a full-wave rectifier 2, a phase comparator 3, a low-pass filter 4, a voltage-controlled oscillator 5, and a phase shifter 6. We are prepared. A binary baseband signal output from a predetermined phase detector is input to a 1-bit A/D converter 1 and also to a full-wave rectifier 2. In the full-wave rectifier 2, the binary baseband signal m
is doubled and the timing signal is extracted. This extracted signal is input to a phase comparator 3, a low pass filter 4 and a voltage controlled oscillator 5.
forms a phase synchronization system, and the voltage controlled oscillator 5
is phase-synchronized with the extraction timing signal,
Furthermore, a reproduction timing signal with jitter components suppressed can be obtained due to equivalent narrow band characteristics. This reproduction timing signal is input to the phase shifter 6, where the phase is adjusted and the 1-bit A/
It is input to the D converter 1. In the 1-bit A/D converter 1, the binary baseband signal m
is sampled and shaped by the timing signal input from the phase shifter 6, and becomes a data signal.
Output as X ₁ . In this conventional timing synchronization circuit, the reproduction timing signal output from the voltage controlled oscillator 5 is transmitted via the phase synchronization system, and although its timing frequency matches the frequency of the timing signal of the baseband signal, Regarding the phase, there is generally a quasi-fixed residual phase difference between the baseband signal and the timing signal, and in the A/D converter 1, the baseband signal m is sampled and shaped at the optimal timing. It has not become a condition. For this reason, it is necessary to artificially adjust the phase of the reproduction timing signal output from the voltage controlled oscillator 5 and input to the A/D converter 1 using the phase shifter 6. The drawback is that it is not easy. (Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, and to enable the baseband signal to be sampled and shaped at the optimal timing in the A/D converter at all times without requiring artificial phase adjustment operations. An object of the present invention is to provide a timing synchronization circuit that can automatically control and adjust the phase of a reproduced timing signal and maintain it. (Structure of the Invention) A timing synchronization circuit of the present invention is a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited baseband signal, comprising: a fixed frequency oscillator that generates a timing original signal of the timing signal; A variable phase shifter that automatically controls and adjusts the phase of the timing original signal using a predetermined phase control signal; and sampling and shaping of the baseband signal using the timing signal outputted via the variable phase shifter. a polarity determination circuit that determines the polarity of the differential coefficient of the baseband signal at the sampling point of the A/D converter by referring to the data signal output from the A/D converter; By referring to the polarity discrimination signal output from the polarity discrimination circuit and performing polarity control calculation processing on the data signal for determining the position of the baseband signal among the data signals output from the A/D converter. A logic circuit that generates the phase control signal; and an automatic timing control system that includes: (Embodiments of the Invention) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the main parts of the first embodiment of the present invention. Before describing this embodiment, please refer to the diagrams for explaining the operation of the timing synchronization system shown in FIGS. 4a and 4b. The operating principle of the present invention will now be explained. In FIG. 4a, m ₁ to _{m 4} indicate waveforms of band-limited binary baseband signals, and this band-limited binary baseband signal is sampled in a predetermined 2-bit A/D converter. and identified by the reference levels L ₁ , L ₂ and L ₃ shown in FIG. 4a, the data signals X ₁ and
converted to X ₂ . The relationship between this baseband signal m and data signals X ₁ and X ₂ is as shown in Table 1 below.

[Table] T _-1 , T ₀ and T ₁ in Fig. 4b represent the optimum sampling points between the three time slots, and now the signals m ₁ to _{m 4} are the sampling points.
When sampled at T _-1 ~ _{T 1} , the baseband signal position (A _-1 , a _-1 , B ₀ , b ₀ , C ₁ , c ₁ )
The data signal X ₂ that determines the ``1'' or ``0'' is output with equal probability, but if it is sampled at the timing of +△t or -△t, _the data signal The output will be as shown in the table below.

[Table] From Table 2 above, for data signal X ₂ ,
In the case of the baseband signal waveform m ₁ to _{m 2} , that is, the baseband signal in which the polarity of the differential coefficient at time T ₀ is positive, it is always “1” when the sampling point reaches +Δt, and on the contrary, When it reaches −Δt, it always becomes “0”. On the other hand, in the case of waveforms m ₃ to _{m 4} , that is, baseband signals in which the polarity of the differential coefficient at time T ₀ is negative, a data signal X ₂ of the opposite polarity to the waveforms m ₁ to m ₂ is obtained. Therefore, by inverting the polarity of the data signal X ₂ , the same data signal as in the case of waveforms m ₃ to _{m 4} can be obtained. Therefore, if the polarity of the differential coefficient of the baseband signal at time T ₀ is determined as described above, and the predetermined logical operation is performed on the data signal X ₂ by referring to the determination result, the output signal will be , it is clear that it can serve as an error signal for detecting the deviation of the sampling point. Next, the operation of the first embodiment of the present invention shown in FIG. 2 will be described. As shown in the figure, the timing synchronization circuit of this embodiment includes a 2-bit A/D converter 7, a polarity discrimination circuit 8, a logic circuit 9, a low-pass filter 10, a fixed frequency oscillator 11, A variable phase shifter 12 is provided. Further, one embodiment of each of the polarity discrimination circuit 8 and the logic circuit 9 is shown in FIG. In Figure 3,
The polarity discrimination circuit 8 is formed by D-type flip-flops 13 to 15 and an amplitude comparator 16, and the logic circuit 9 is formed by D-type flip-flops 17 to 18, 25 and an OR/NOR gate 19.
, AND gates 20-21, 24, and OR gates 22-23. The first embodiment shown in FIG. 2 is an example of a timing synchronization circuit that supports a binary baseband signal, and the band-limited binary baseband signal m is
The data signal is inputted to the 2-bit A/D converter 7 and sampled and shaped by the timing signal sent via the variable phase shifter ₁₂ .
and output as X ₂ . The operation of the 2-bit A/D converter has already been explained with reference to FIGS. 4a and _4b and Table ₁ , and the baseband signal m _is set to Identified, data signals X ₁ and X ₂
is converted to The data signal X ₁ is output as a predetermined data signal and is simultaneously input to the polarity determination circuit 8 . The polarity discrimination circuit 8 has a function of discriminating the band-limited baseband waveforms m ₁ to _{m 4} , and the output signal G becomes “1” in the case of the waveforms m ₁ to _{m 2} . The signal becomes "1" in the case of waveforms _m3 to _m4 . Logic circuit 9 has 2 bits A/
The data signal X ₂ input from the D converter 7 is
When the signal is “1”, the polarity is inverted, and when both the signals G and are “0”, the waveform is
It is equipped with a circuit that holds the nearest past data signal X ₂ with a waveform of one of m ₁ to m ₄ ,
As a result, the output of the logic circuit 9 contains 2 bits A/
A predetermined error signal is obtained that detects the deviation of the sampling point in the D converter 7. This error signal is passed through the low-pass filter 10 to the variable phase shifter 12 as a phase error signal of the timing signal synchronization circuit.
By supplying the signal to the 2-bit A/D converter 7, a timing synchronization system is formed, and the timing signal is always supplied to the 2-bit A/D converter 7 at the optimum timing. The variable phase shifter 12 includes, for example, a variable capacitance diode and an inductor, and shifts the phase by changing the bias to the variable capacitance diode. FIG. 3 shows one embodiment of the polarity discrimination circuit 8 and the logic circuit 9 as described above. In the polarity discrimination circuit 8, in response to the input of the data signal _X1 and the timing signal T,
3, 14, and 15 operate as 3-bit memories, and D-type flip-flops 12 and 15
The outputs Y ₁ and Y _-1 are input to the amplitude comparator 16. The amplitude comparator 16 has a function of determining the polarity of the differential coefficient of the baseband signal at the sampling point _T0 in the 2-bit A/D converter 7, and compares data at the sampling points T _{-1 and} T1. Accordingly, the polarity of the differential coefficient is determined. That is, “0” at data output Y _-1 and Y ₁
When changing from "1" to "1", the polarity of the differential coefficient is positive, and when changing from "1" to "0", the polarity of the differential coefficient is negative. The amplitude comparator 16 outputs the signal G and which determines the polarity, but when the waveform of the baseband signal is _m1 to _m2 , G is "1".
, and becomes "1" when m ₃ to _{m 4} . On the other hand, data signal X ₂ is input to OR/NOR gate 19 via D-type flip-flops 17 and 18, the outputs of which are input to AND gates 20 and 21, respectively. The gate circuit formed by the AND gates 20 and 21 and the OR circuit 23 outputs the data signal X 2 as is when the signal G is "1", and outputs the data signal X ₂ as it is when the signal G is "1 _" . It works by inverting the polarity and outputting it. Furthermore, the AND gate 24 operates to output the timing signal T when either the signals G and are "1", and output 0 when the signals G and are both "0".
Therefore, when the waveform of the baseband signal is in the state of m ₁ to _{m 4} , the output of the OR gate 23 is output as is to the output of the D-type flip-flop 25, and the waveform is in the state of m ₁ to m ₄ . In cases other than the current state, it operates to hold the data signal X ₂ of any of the past waveforms m ₁ to m ₄ closest to the current time. However, such a holding function when the differential coefficient is 0 improves the characteristics, and there is no problem with the operation of the present invention even if it is not added. Note that FIG. 5 shows an embodiment of the amplitude comparator 16, which includes OR/NOR gates 26, 27,
AND gates 28 and 29. Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing the main part of the second embodiment, and is an example in which the baseband signal has four values. As shown in the figure, the second embodiment includes a 3-bit A/D converter 30 and a polarity determination circuit 31.
, a logic circuit 32 , a low-pass filter 33 , a variable phase shifter 34 , and a fixed frequency oscillator 35 . Further, FIG. 7 shows the relationship between the four-level baseband signal input and the data signals X ₁ to X ₃ as the conversion outputs of the 3-bit A/D converter 30. In FIG. 6, in the case of a four-level baseband signal, _the data signal for determining the position of the input baseband signal is X ₃ as shown in FIG. is input.
The polarity determination circuit 31 outputs a signal G and having the same function as the polarity determination circuit in the first embodiment described above, and inputs it to the logic circuit 32. An error signal for detecting the deviation of the sampling point is obtained at the output of the logic circuit 32, and this error signal is sent to the variable phase shifter 34 via the low-pass filter 33 as a phase error signal. This variable phase shifter 34 outputs the output signal of the fixed frequency oscillator 35 to the polarity discriminator 31,
Logic circuit 32 and 3-bit A/D converter 3
0 and a synchronization system for the timing signal is formed, as in the first embodiment. FIG. 8 is a block diagram showing the main parts of an embodiment of the polarity discrimination circuit 31 and the logic circuit 32, in which the logic circuit 32 includes the logic circuit 9 used in the first embodiment described above and its configuration. and the operation is exactly the same. In the figure, a polarity discrimination circuit 31 is formed by D-type flip-flops 36 to 41 and an amplitude comparator 42, and a logic circuit 32.
is a D type flip-flop 43-44,5
2, OR/NOR gate 45, AND gate 4
6 to 47, 50 and OR gates 48 to 49. In FIG. 8, data signals X ₁ and X ₂ input to the polarity discrimination circuit 31 and a timing signal T
Correspondingly, D type flip flop 3
The outputs of 6 and 39 have data signals X ₁ and
Data Y ₁ at sampling point T ₁ of X ₂ is obtained, and D type flip-flops 38 and 41
Data Y _-1 at the sampling point T _-1 of the data signals X ₁ and X ₂ is obtained as the output. These data Y1 _and Y _-1 are input to the amplitude comparator 42, and their levels are subjected to logical operation processing to determine the polarity of the differential coefficient of the 4-value baseband signal input to the 3-bit A/D converter 30. is determined. Now, let the 4-value signal at T _-1 be E _-1 , and the 4-value signal at T ₁
Assuming that the value signal is E ₁ , the amplitude comparator 42 calculates E ₁ -E _-1 = M, and M is positive, that is, T ₀
When the differential coefficient at time is positive, the signal G is “1”
When M is negative, that is, the differential coefficient at _T0 is negative, the signal is output as "1". Note that E _-1 and E ₁ above are D type flip-flops 36, 38, 39 and 4.
1 is obtained as part of the logic operation processing in the amplitude comparator 42, as described above. In addition, in the above, the present invention is defined as binary and quadrilateral.
Although an embodiment has been described in which the application is applied to a timing synchronization circuit corresponding to a baseband signal of two values, the scope of application of the present invention is not limited to the case of the baseband of two values and four values. Needless to say, the method can also be applied to multilevel baseband signals. In addition, in the above description, the operation is explained in correspondence with the digital carrier wave transmission method as the applicable area of the present invention, but the applicable area of the present invention is not limited to this, and the application area of the present invention is not limited to this. It can also be effectively applied to. Of course, it goes without saying that the Herok diagrams and the like used to explain the first and second embodiments do not limit the present invention. (Effects of the Invention) As described above in detail, the present invention provides a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited baseband signal. By using an automatic timing control system that includes a variable phase shifter that automatically controls and adjusts the phase of the timing original signal output from a fixed frequency oscillator, it is no longer necessary to manually adjust the phase, which is difficult to operate as in the past. This has the advantage that the optimum sampling timing for the baseband signal can be maintained at all times without having to do so.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a conventional timing synchronization circuit, FIG. 2 is a block diagram showing the main parts of the first embodiment of the present invention, and FIG. 3 shows a polarity discrimination circuit and a logic circuit. FIGS. 4a and 4b are explanatory diagrams of the operation of the timing synchronization circuit, FIG. 5 is a block diagram of an example of the amplitude comparator, and FIG. 6 is a main part of the second embodiment of the present invention. Block diagram showing 7th
The figure shows the correspondence relationship between the four-level baseband signal and the data signal, and FIG. 8 shows another example of the polarity discrimination circuit,
FIG. 2 is a block diagram of an example of a logic circuit. In the figure, 1...1-bit A/D converter,
2...Full wave rectifier, 3...Phase comparator, 4,1
0,33...Low pass filter, 5...Voltage controlled oscillator, 6...Phase shifter, 7...2 bit A/D converter, 8,31...Polarity discrimination circuit, 9,32
...Logic circuit, 11,35...Fixed frequency oscillator, 12,34...Variable phase shifter, 13-15,1
7-18, 25, 36-38, 39-41, 43
~44,51...D type flip-flop,
16, 42...amplitude comparator, 19, 26-27,
45...OR/NOR gate, 20-21, 24,
28-29, 46-47, 50...AND gate,
22-23, 48-49...OR gate.

Claims (1)

[Claims] 1. In a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited baseband signal, a fixed frequency oscillator that generates a timing original signal of the timing signal, and a predetermined phase control for controlling the phase of the timing original signal. a variable phase shifter that automatically controls and adjusts according to a signal; an A/D converter that samples and shapes the baseband signal using a timing signal outputted through the variable phase shifter; and the A/D converter. With reference to the data signal output from the A/D
A polarity determination circuit that determines the polarity of the differential coefficient of the baseband signal at the sampling point of the converter, and a polarity determination signal output from the polarity determination circuit to determine the polarity of the data signal output from the A/D converter. A timing synchronization circuit comprising: a logic circuit that generates the phase control signal by performing polarity control arithmetic processing on a data signal that determines the position of the baseband signal; .