JPH0326934B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a timing synchronization circuit, and particularly to a timing synchronization circuit for regenerating a timing signal for converting a demodulated signal from a band-limited multilevel baseband signal into a predetermined digital signal. , relating to improvements in timing synchronization circuits.

(Prior Art) In a demodulator used in a digital carrier wave transmission system, a predetermined timing signal is generally required in order to convert a demodulated signal into a digital signal. Polyphase phase modulation (hereinafter referred to as polyphase modulation)
In a digital carrier wave transmission system using a PSK (abbreviated as PSK) method or a multi-value quadrature amplitude modulation (hereinafter abbreviated as multi-value QAM) method, conventionally, as a means for reproducing the timing signal from a band-limited multi-value baseband signal, As an example, the timing synchronization circuit shown in FIG. 1 is used.

The timing synchronization circuit shown in FIG. 1 corresponds to the case where the modulation method is 8PSK or 16QAM, and the 3-bit A/D converter 1,
It includes a polarity determination circuit 2, a logic circuit 3, a low-pass filter 4, and a voltage controlled oscillator 5. In the figure,
For example, a 16QAM baseband signal m demodulated and band-limited by a predetermined phase detector is input to a 3-bit A/D converter 1, sampled and shaped by a timing signal input from a voltage controlled oscillator 5, and then Reference level L ₁ in figure a,
L ₂ , L ₃ , L ₄ , L ₅ , L ₆ and L ₇ are converted into data signals X ₁ , X ₂ and X ₃ . The relationship between this baseband signal m and data signals X ₁ , X ₂ and X ₃ is shown in FIG. Here, X ₃ is a position determination signal for determining the position of the 4-level baseband signal.

In Figure 3b, T _-1 , T ₀ and T ₁ are 3
It represents the optimal sampling point for the 4-level baseband signal between time slots,
Also, (A _-1 , A′ _-1 , A″ _-1 , A
_-1 ), (B ₀ ,B′ ₀ ,B″ ₀ ,B ₀ ) and (C ₁ ,C′ ₁ ,
C″ ₁ , C ₁ ) represent the convergence point of the timing synchronization circuit at each reference level of _the four-level baseband signal sampled at T _-1 , T ₀ and T ₁ , respectively. .respectively reference levels L ₁ , L ₃ , L ₅ and L ₇
At convergence points B ₀ , _{B ′ 0} , _{B ″ 0 and B 0} corresponding to _m7 and _m8
is displayed in a form showing only the vicinity of the focal point. In addition, the convergence points A _-1 , A _{' -1} , A′ _-1 , corresponding to each level at other sampling points T -1 and T ₁
A″ _-1 , and A _-1 and C ₁ , C′ ₁ , C″ ₁ and C
₁ , a portion of the neighboring waveform of the 4-level baseband signal is also displayed.

As is clear from FIGS. 3a and b and FIG. 4, the convergence point at the sampling point T ₀
The data signal X ₃ discriminated at B ₀ , B′ ₀ , B″ ₀ and B ₀ is expressed as shown in FIG. 5 when sampled at the timing of T ₀ ±ΔT before and after T ₀ . From figure 5, data signal X ₃
In the baseband signal waveforms m ₁ to _{m 4} , that is, when the polarity of the time differential coefficient at the sampling point T ₀ is positive, the sampling point is T ₀
When +ΔT, X ₃ is always “1”, and on the contrary, T ₀
-ΔT, X ₃ is always “0”.

On the other hand, when the polarity of the time differential coefficient at the baseband signal waveforms m ₅ to _{m 8} , that is, the sampling point T ₀ is negative, the data signal has a polarity opposite to that of the baseband signal waveforms m ₁ to m ₄ described above. X ₃ is obtained, so the data signal X ₃ for this m ₁ to _{m 4} case
If the polarity of is reversed, a data signal equivalent to that of waveforms m ₅ to _{m 8} will be obtained. In this way, by determining the polarity of the differential coefficient at the sampling point T ₀ of the multilevel baseband signal and performing logical operations on _the data signal X ₃ with reference to the determination result, the output signal will be This can serve as an error signal for detecting deviation.

The polarity discrimination circuit 2 in FIG. 1 is for discriminating the multilevel baseband signal waveforms m ₁ to m ₈ . The signal G becomes "1" in the case of the waveforms m ₁ to m ₄ , and the signal G becomes "1" in the case of the waveforms m 1 to m ₄ . In case of ₈ , it becomes “0”. logic circuit 3
inverts the polarity of the data signal _X3 input from the 3-bit A/D converter 1 when the signal is "1", and when both the signals G and G are "0", the waveforms _m1 to It has the _function of holding the nearest past _data signal
An error signal for detecting the time shift of sampling points in the D converter 1 is obtained. This error signal is passed through a low frequency three-wave generator 4 to a voltage controlled oscillator 5.
A timing signal that can maintain the aforementioned optimum sampling point by supplying it as a phase control signal to the voltage control oscillator 5 is outputted from the voltage controlled oscillator 5 and supplied to the 3-bit A/D converter.

FIG. 6 shows a specific example of the polarity discrimination circuit 2 and the logic circuit 3.
9 and 26 are D type flip-flops, 1
7 is an amplitude comparator, 20 is an OR/NOR gate, 21
~22 and 25 are AND gates, 23~24 are
It is an OR gate. In polarity determination circuit 2, data signals _X1 and _X2 are input to flip-flops 11 and 14, and timing signal T sent from voltage controlled oscillator 5 is input to flip-flops 11-16. flipflop 11
and 14 outputs each have a data signal X ₁
The data of data signals X 1 and X ₂ at time T ₁ are obtained, and the data of data signals X ₁ and X ₂ at time T _-1 are obtained at the outputs of flip-flops 13 and 16, respectively. These data signals X ₁ and X ₂
Both data Y ₁ and Y _-1 corresponding to are input to the amplitude comparator 17, and the amplitude comparator 17 determines the polarity of the differential coefficient of the multilevel baseband signal.
Now, the 4-level baseband signal at time T _-1 is a _-1
and the 4-level baseband signal at T ₁ is a ₁
Then, in the amplitude comparator 17, a ₁ −a ₋₁
= M is calculated, and if the value of M is positive, that is, the differential coefficient at T ₀ is positive, the signal G is output as "1", and the value of M is negative, that is, the differential coefficient at T ₀ . If is negative, the signal is output as "1". Note that a _-1 and a ₁ are obtained from the outputs of the flip-flops 11, 13, 14, and 16 by logical operations in the amplitude comparator 17.

The above explanation is an outline of the operation of a conventional timing synchronization circuit that reproduces a timing signal from a band-limited multilevel baseband signal. Because it is closely related to the operation, Figure 1,
This was specifically explained with reference to FIGS. 3, 4, 5, and 6. However, the above
In a timing synchronization circuit that reproduces a timing signal for digitizing a four-level baseband signal that supports the 16QAM system, three series of data signals X ₁ , X ₂ and Of X ₃ , two series of data signals, X ₁ and X ₂ , are input to a polarity discrimination circuit for polarity discrimination. Generally, as the number of multi-value baseband signals increases, the number of data signal series output from the n-bit A/D converter also increases to n series, and the number of data signal series output from the n-bit A/D converter increases to n series. The data signal also increases corresponding to n-1. Therefore, there is a drawback that the circuit configuration of the polarity determination circuit, which is one of the main components of the timing synchronization circuit, becomes complicated.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide an A/D converter for sampling and shaping a multi-value baseband signal in order to reproduce a timing signal for digitizing the multi-value baseband signal. To provide a timing synchronization circuit that can simplify the circuit configuration of the polarity discrimination circuit by using a data signal identified by a central reference level value as a reference signal for polarity discrimination for the polarity discrimination circuit. be.

(Structure of the Invention) The timing synchronization circuit of the present invention is a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited multilevel baseband signal.
A timing signal generation circuit formed so that the output phase of the timing signal is automatically controlled and adjusted by a predetermined phase control signal, and a timing signal output from the timing signal generation circuit, an n (an integer of 3 or more) bit A/D converter that samples and shapes a value baseband signal; and the n-bit A/D converter of a predetermined n series of data signals output from the n-bit A/D converter. Determining the polarity of the differential coefficient of the previous multilevel baseband signal at the sampling point of the n-bit A/D converter by referring to a specific series of data signals that are identified and output by the central reference level value in the converter. a polarity discrimination circuit for determining the multilevel baseband signal among the predetermined n series of data signals output from the n-bit A/D converter by referring to the polarity discrimination signal output from the polarity discrimination circuit; a logic circuit that generates the phase control signal by performing polarity control arithmetic processing on a specific series of data signals for position determination;

(Embodiments of the Invention) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the main part of the first embodiment of the present invention, in which a voltage controlled oscillator whose phase is controlled and adjusted by the phase control signal is used as the control means for the output phase of the timing signal. , shows an example of a timing synchronization circuit corresponding to a four-level baseband signal.

As shown in FIG. 2, the first embodiment has three
Bit A/D converter 6 and polarity discrimination circuit 7
, a logic circuit 8 , a low-pass filter 9 , and a voltage-controlled oscillator 10 .

In FIG. 2, a band-limited 4-level baseband signal m is input to a 3-bit A/D converter 6, sampled and shaped by a timing signal sent from a voltage controlled oscillator 10, and converted into data signals X ₁ , Output as X ₂ and X ₃ . 3
The operation of the bit A/D converter 6 is as described in the prior art example. The data signal _X1 is output as an original data signal and is also input to the polarity determination circuit 7 as a reference number for polarity determination. A block diagram of one embodiment of the polarity discrimination circuit 7 is shown in FIG. In FIG. 8, 33 to 35 are D type flip-flops, and 36 is an amplitude comparison circuit.

In the polarity discrimination circuit 7 shown in FIG. 8, the data signal _X1 is input to the flip-flop 33,
The timing signal T sent from the voltage controlled oscillator 10 is applied to the flip-flops 33, 34 and 3.
5 is input. Flip-flop 33 and 3
Data Y 1 and Y _-1 at time T ₁ and time T _-1 of data signal X ₁ are obtained at the output of data signal X ₁ , respectively, and both are input to amplitude comparator 36 . In this case, the difference from the conventional example described above is that the amplitude comparator 36
The data Y _-1 and Y ₁ input to the data signal
The point is that the data corresponds only to _X1 . In the amplitude comparator 36, the above data Y _-1 and
Input Y ₁ to calculate the amplitude of the binary baseband signal at T _-1 and T ₁ through a predetermined logical operation.
b _-1 and b ₁ are extracted, and b ₁ -b _-1 =M is calculated. Here again, since b ₁ and b _-1 are created from the data signal X ₁ , they are signals that have the same amplitude level and only change in polarity. If the value of M is positive, that is, the differential coefficient of the baseband signal at T ₀ is positive, the signal G is output as "1", and the value of M is negative, that is, the baseband signal at T ₀ . If the differential coefficient of is negative, the signal is output as "1". To further explain this using FIG. 3, the baseband signal changes from A _-1 or A' _-1 to C'' or C ₁
, and from A″ _-1 or A _-1 ,
When it changes to C ₁ or C' ₁ , that is, when the polarity of X ₁ is reversed, a positive or negative value is obtained as the value of the differential coefficient M of the baseband signal, so depending on the polarity of X ₁ , Baseband signal waveform m ₁
It becomes possible to detect the differential coefficient of ~ _m8 .

Note that the probability that the differential coefficient can be detected from the baseband signal is determined by the probability that the polarity of X ₁ is reversed, and its value is 1/2. This value is
It does not change even when the number of multivalues increases, and is a sufficient value for the circuit to operate normally and stably.

The signal G output from the polarity discrimination circuit 7 is input to the logic circuit 8.
As an example, the logic circuit 3 cited when explaining the conventional timing synchronization circuit shown in FIG. 6 can be directly referred to. In the logic circuit ₃ of FIG. 6, the data signal
The timing signal T sent from the D-type flip-flops 18 and 19 and the AND gate 25 is inputted to the D-type flip-flops 18 and 19 and the AND gate 25. On the other hand, the signals G and sent from the polarity discrimination circuit 7 are input to AND gates 21 and 22 and an OR gate 23.
The output of the D-type flip 19 has a data signal.
Data at T ₀ of X ₃ is obtained, OR/NOR
Through the gate actions of the gate 20 and AND gates 21, 22, and 24, when the signal G is " ₁ ", the polarity of the data signal
When the signal is "1", the polarity of the data signal _X3 is inverted and output. Also, AND gate 2
When either the signal G or is "1", the timing signal T is outputted to the output of 5.
When signals G and both are "0", timing signal T is not output. Therefore, D type
The output of the flip-flop 26 is as shown in FIG.
and b, the waveforms of the baseband signals at the convergence points B ₀ , B′ ₀ , B″ ₀ and B ₀ corresponding to timing T ₀ are in the state indicated by m ₁ to m ₈ In this case, the output of the OR gate 24 is output as is, and the waveform of the baseband signal is at the convergence points B ₀ , B′ ₀ , B″ ₀ and B
₀ , if the state is not as shown in FIG. 3a, the data signal _X3 is held in correspondence with the past waveform state closest to the current time. As a result, an error signal for detecting the deviation of the sampling point is generated at the output of the logic circuit 3, output as a phase control signal for the timing signal, and sent to the voltage controlled oscillator 10 via the low-pass filter 9. It will be done.

The oscillation frequency of the voltage controlled oscillator 10 is shaped and adjusted by the phase control signal, and the phase of its oscillation output is controlled in a manner corresponding to the integral value of the phase control signal. The output of the voltage controlled oscillator 10 is sent as a predetermined reproduction timing signal to a 3-bit A/D converter 6, and is also input as a timing signal T to a polarity determining circuit 7 and a logic circuit 8. Obviously, in FIG. 2, the logic circuit 8 (same as the logic circuit 3), the low-pass filter 9, and the voltage controlled oscillator 10 implement a synchronization system of timing signals using the band-limited baseband signal as a reference signal. The 3-bit A/D converter 6 is always supplied with a timing signal for sampling shaping from the voltage controlled oscillator 10 at the optimum timing. Note that the holding function when the differential coefficient is 0 in the logic circuit 8 improves the synchronization characteristics of the timing synchronization system itself, and there is no problem with the operation of the present invention even if it is not added.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing the main parts of the second embodiment, including a 3-bit A/D converter 27, a polarity discrimination circuit 28, a logic circuit 29, and a low-pass filter 3.
0, fixed frequency oscillator 31, and variable phase shifter 32
It is equipped with

The difference between this second embodiment and the first embodiment described above lies in the timing signal synchronization system that controls the phase of the timing signal. In the second embodiment, the timing signal synchronization system includes logic circuit 2.
9 (same as the logic circuit 3), a low-pass filter 30 and a variable phase shifter 32, and the oscillation output signal of the fixed frequency oscillator 31 is
In the variable phase shifter 32 whose transmission phase amount is controlled by the phase control signal sent from 0, the phase is controlled and adjusted to a predetermined phase, and 3 is used as a timing signal for sampling shaping with respect to the baseband signal.
The signal is input to the bit A/D converter 27 and sent to the polarity determination circuit 28 and logic response 29. In addition, the 3-bit A/D converter 27,
The operations of the polarity determination circuit 28 and the logic circuit 29 are the same as in the first embodiment described above.

In the above first and second embodiments, the present invention has been described with respect to a timing synchronization circuit that corresponds to a four-value baseband signal as a multi-value baseband signal. It is not limited to cases corresponding to baseband signals, and can generally be applied to multilevel baseband signals of four or more levels, for example, 64
In the case of a value QAM signal, a 4-bit A/D converter is used as the A/D converter, and the data signal output from this 4-bit A/D converter is
Data signal X ₁ corresponding to X ₁ , X ₂ , X ₃ and X ₄
A timing synchronization circuit is formed in such a way that the data signal X4 is sent to the polarity discrimination circuit for polarity discrimination, and the data signal _X4 is sent to the logic circuit for position discrimination.
Generally, as a special case for binary baseband signals in 4-phase PSK and 4-level QAM, 8-phase
In the case of 4-level baseband signals in PSK and 16-level QAM, and also for multi-level baseband signals in 16QAM, 64QAM, etc., the data signal for polarity discrimination to the polarity discrimination circuit is as follows:
In the A/D converter, the desired timing synchronization circuit can be formed by referring only to the data signal identified by the central reference level value.

In addition, in the above description, the operation has been explained with the digital carrier wave transmission system as the main target area as the application area of the present invention, but the application area of the invention is not limited to this, and baseband Needless to say, the present invention is also applicable to transmission systems. Of course, it is clear that the block diagrams and the like used to explain the first and second embodiments do not limit the present invention.

(Effects of the Invention) As described above in detail, the present invention provides a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited baseband signal, which includes a voltage controlled oscillator or a variable phase shifter. By sending only one specific series of data signals as a reference signal to the polarity discrimination circuit, which is a component of the synchronization system, for polarity discrimination,
This has the effect that the circuit configuration of the polarity discrimination circuit is simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part of a conventional timing synchronization circuit, FIG. 2 is a block diagram showing the main part of the first embodiment of the present invention, and FIGS. 3a and 3b are
An explanatory diagram of the operation of the timing synchronization circuit, FIG. 4 is a correspondence diagram between the baseband signal m and data signals X ₁ , X ₂ and X ₃ , and FIG. 5 is a state diagram of the data signal X ₃ .
FIG. 6 is a block diagram of an example of a polarity discrimination circuit and a logic circuit, FIG. 7 is a block diagram showing main parts of a second embodiment of the present invention, and FIG. 8 is a block diagram of an example of a polarity discrimination circuit and a logic circuit.
FIG. 2 is a block diagram of one embodiment of a polarity discrimination circuit used in the embodiment of FIG. In the figure, 1, 6, 27...3-bit A/D converter,
2, 7, 28...Polarity discrimination circuit, 3, 8, 29...
...Logic circuit, 4,9,30...Low-pass filter, 5,
10... Voltage controlled oscillator, 11, 12, 13, 1
4, 15, 16, 18, 19, 26, 33, 3
4,35...D type flip-flop, 1
7, 36...amplitude comparison circuit, 20...OR/NOR
Gate, 21, 22, 25...AND gate, 2
3,24...OR gate.

Claims (1)

[Claims] 1. In a timing synchronization circuit that reproduces a predetermined timing signal from a band-limited multilevel baseband signal, the output phase of the timing signal is automatically controlled by a predetermined phase control signal. n (an integer of 3 or more) sampling and shaping the multilevel baseband signal using a timing signal generation circuit formed to be adjusted and a timing signal output from the timing signal generation circuit;
a bit A/D converter and the n-bit A/D converter;
Of the predetermined n series of data signals output from the D converter, the n A polarity discrimination circuit that discriminates the polarity of the differential coefficient of the multi-level baseband signal at the sampling point of the bit A/D converter, and a polarity discrimination signal output from the polarity discrimination circuit to determine the polarity of the n-bit A/D converter. The phase control signal is generated by performing polarity control calculation processing on a specific series of data signals for determining the position of the multilevel baseband signal among the predetermined n series of data signals output from the converter. A timing synchronization circuit comprising a logic circuit. 2. In the timing signal generation circuit, a voltage controlled oscillator whose oscillation output phase is controlled by the phase control signal is applied as a control means for the output phase of the timing signal. timing synchronization circuit. 3. In the timing signal generation circuit, as a control means for the output phase of the timing signal, in order to control the output phase of a predetermined fixed frequency oscillator,
The timing synchronization circuit according to claim 1, characterized in that a variable phase shifter whose transmission phase amount is controlled by the phase control signal is applied.