JPH0118616B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical field) The present invention relates to A/D in a multilevel quadrature amplitude modulation system.
This invention relates to a method of configuring a carrier recovery circuit using a converter and a digital signal processing circuit. (Background Art) In a multi-value quadrature amplitude modulation method, an A/D converter is used as a circuit to reproduce a carrier wave for synchronous detection, and a multi-value signal is identified by an A/D converter, and the identification result is used to generate a digital processing circuit (such as a ROM, a logic circuit, etc.). ) has been devised to obtain a carrier wave phase control signal. (For example, Japanese Patent Application No. 58-21604) In order to improve the synchronization pull-in characteristic of the carrier phase, this carrier regeneration circuit used only signal points with equal distances from the in-phase axis and the orthogonal axis as control information, so during phase synchronization, the demodulation When the signal is stationary with little intersymbol interference, the loop gain of the phase synchronization circuit decreases and reproduced carrier wave jitter increases. (Objective of the Invention) In order to solve these drawbacks, the present invention is designed to solve the following problems: When the amount of intersymbol interference of the demodulated signal is large at the time of synchronization pull-in and synchronization, the in-phase Only points having the same distance from the axis and the orthogonal axis are selected and used as phase control information. On the other hand, when the intersymbol interference of the demodulated signal is small during synchronization (in steady state), by using all points as control information, it is possible to improve the loop gain and the C/N of the recovered carrier wave in steady state. To provide a carrier wave regeneration circuit that can automatically switch control information based on the result of exclusive OR of the upper (n+1)th bit and the upper (n+2)th bit based on the identification result of the output of an A/D converter. There is a particular thing. (Structure and operation of the invention) The present invention will be explained below based on the drawings. The configuration of the present invention is shown in FIG. In the same figure,
1 is an input terminal, 2 and 2' are quadrature phase detectors, 3 and 3' are low-pass filters for removing harmonics, 4 and 4' are DC amplifiers, and 5 and 5' are (n+2) bit A/
D converter, 16 is a loop filter (LPF), 17
is a voltage controlled oscillator (VCO), 18 is a π/2 phase shifter, and 22 is a VCO control circuit. To explain the operating principle, a quadrature amplitude modulated wave of 2 ²ⁿ values is input through input terminal 1, and quadrature phase detectors 2 and 2'
The ²²ⁿ value baseband signal of the in-phase and quadrature components obtained through the filter is passed through harmonic removal low-pass filters 3, 3', and then passed through DC amplifiers 4, 4' to a predetermined level, and its gain is adjusted. and adjust the offset. By passing the signal through the (n+2) bit A/D converters 5, 5', the upper n
The bits directly serve as the identification results. The upper n bits, the upper (n+1)th bit, and the upper (n+
2) Take out the VCO control signal by passing the bit through the VCO control circuit 22. The signal is smoothed through a loop filter 16, and the carrier wave is regenerated by controlling the VCO 17. Specifically, the VCO control circuit generates a carrier phase error signal (signal 1) and a signal (signal 2) for detecting the state of the carrier regeneration loop based on the output of the (n+2)-bit A/D converter 22. ) and
A signal that selects only signals having the same distance from the in-phase axis and the orthogonal axis (signal 3) is detected, the logical sum of signals 2 and 3 is performed, and the logical product of this result and the timing signal is used to generate a signal. 1 is sampled and held, and the voltage controlled oscillator 22 is controlled. Next, an embodiment of the present invention will be described based on FIGS. 2 to 4, taking a 16QAM signal (n=2) as an example. FIG. 2 is a configuration diagram when a 16QAM signal is used. In the figure, 6, 7, 9, 10 are exclusive OR (EX-OR), 8, 12 are exclusive inverse OR (EX-NOR), 11, 14 are 2-input AND,
13 is a two-input OR, 15 is a D-type flip-flop, 19 is a timing signal input terminal, and 21 is a circuit that selects only signal points that are the same distance from the in-phase axis and the orthogonal axis. Note that the other configurations are the same as in FIG. 1. In the figure, the four-value baseband signal of in-phase and quadrature components obtained through quadrature phase detectors 2 and 2' is passed through low-pass filters 3 and 3' for harmonic removal to form the level diagram shown in Figure 3. Naru-sama,
Adjust the gain and offset of DC amplifiers 4, 4'. That is, when converting to a 4-bit digital signal, the discrimination level of the most significant bit (referred to as Path1 discrimination) is set so as to divide the A/D converter input voltage into two equal parts. Identification of the upper 2nd bit (referred to as Path 2 identification) is performed by setting the level so as to divide the input voltage into 4 equal parts, so that the upper 2 bits directly become the identification result of the 4-value signal. The identification of the upper 3rd bit (referred to as Path 3 identification) is performed by setting the input voltage to be divided into 8 equal parts, detecting the deviation direction of the signal point from the steady state, and then identifying the upper 4th bit (referred to as Path 3 identification). ) is set to divide the input voltage into 15 equal parts, and detects the amount of deviation of the signal point from the steady state. Next, as shown in Figure 4, the quadrant of the signal point is determined based on the in-phase and quadrature components Path1 values (S ₁₁ A, S ₁₂ ), and the intersymbol interference is determined using the Path 3 values (S ₃₁ , S ₃₂ ). By determining the direction of the carrier phase error θ, the direction of the carrier phase error θ can be uniquely determined. For example, in the first quadrant, S ₁₁ =S ₁₂ =1, and when S ₃₁ =1, θ=1. Note that in S _ij , i indicates a path number (i=1 to 4 in this embodiment), and j indicates an in-phase component (j=1) or an orthogonal component (j=2). θ=
Table 1 shows the relationship between the direction of intersymbol interference and the direction of intersymbol interference for all quadrants where the value is 1 in a truth table.

[Table] θ is given by the following formula. θ=S ₁₁・S ₁₂・S ₃₁ + S ₁₁・₁₂・₃₁ + ₁₁・S ₁₂・S ₃₁ + ₁₁・₁₂・₃₁ = S ₁₂・S ₃₁ + ₁₂・₃₁ = _{12 31} , that is, the relationship θ= _{12 31} can lead to Therefore, the exclusive inverse OR (EX-NOR) of the value of the first path of the orthogonal component and the value of the third path of the in-phase component
By taking , the carrier phase error signal can be obtained. On the other hand, as an example of the circuit 21 that selects only signal points having the same distance from the in-phase axis and the orthogonal axis, for the in-phase component and the orthogonal component, respectively
This can be realized by taking the exclusive inverted OR 12 of the results of the exclusive ORs 9 and 10 of Path1 and Path2. Also, for the in-phase component and quadrature component, respectively
If the result of the exclusive ORs 6 and 7 of Path3 and Path4 is "1" as shown in FIG. 3, it is determined that the intersymbol interference is small and that it is a steady state. Conversely, if the result of the exclusive OR is "0", it can be determined that the intersymbol interference is large or that the synchronization is out of synchronization. Therefore, when the intersymbol interference is small, by taking the logical sum 13 with the selection signal (output of 12), it becomes "1" regardless of the selection signal, and since the timing signal itself drives the sample and hold circuit 15, all signal points can be used as control information, and the C/N of the reproduced carrier wave in steady state can be improved. On the other hand, when intersymbol interference is large or synchronization is lost, the output of the logical sum 13 becomes the selection signal itself, and by taking the logical sum 14 with the timing signal, the signal point with a large margin against identification errors shown in Fig. 4 ~
By selecting only this and using it as control information, it is possible to prevent a decrease in loop gain and false pull-in due to identification errors due to an increase in carrier phase error. In this way, the control information is automatically switched depending on the magnitude of intersymbol interference, and the control signal obtained in this way is smoothed by passing through the loop filter 16.
The carrier wave can be regenerated by driving the VCO 17. (Effects of the Invention) As explained above, according to the present invention, the identification results of in-phase and quadrature A/D converters are
By taking the exclusive OR of Path3 and Path4, the state of the carrier wave regeneration loop is monitored, and by using it as a control information switching signal, it is possible to improve the C/N of the regenerated carrier wave and the loop gain in steady state, and to achieve synchronization pull-in. When the time or intersymbol interference is large, there is an advantage that a carrier recovery circuit that prevents a decrease in loop gain and false pull-in due to identification errors can be constructed using a small number of digital logic circuits.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 3 is a level diagram of a multilevel signal input to an A/D converter, and FIG. 4 is a diagram showing the relationship between the amount of intersymbol interference and carrier phase error. . 1...Input terminal, 2, 2'...Phase detector, 3,
3'...Low pass filter, 4,4'...DC amplifier, 5,5'...A/D converter, 6,7,9,1
0...exclusive OR, 11,14...2 inputs
AND, 8, 12...exclusive inverted OR, 13...
...2 input OR, 15...D type flip-flop,
16...Loop filter, 17...Voltage controlled oscillator (VCO), 18...π/2 phase shifter, 19...Timing signal input terminal, 20, 20'...A/D
Conversion timing input terminal, 21...Circuit for selecting only signal points having equal distances from the in-phase axis and the orthogonal axis, 22...VCO control circuit.

Claims (1)

[Claims] 1. A quadrature phase detector that receives a multi-value ( ²²ⁿ value) orthogonal amplitude modulated wave as an input signal, a low-pass filter for harmonic removal, a voltage controlled oscillator, a loop filter, and a phase detector. a DC amplifier that sets the 2 ⁿ -value multi-value demodulated signal output from the device to a predetermined level; an A/D converter that converts the multi-value demodulated signal into an (n+2)-bit digital signal; upper n bits, upper (n+1)th bits, and upper (n+2) bits
A control signal for controlling the voltage controlled oscillator is output by performing logical operation on the bit.
A carrier wave generation circuit characterized by comprising a VCO control circuit. 2 The VCO control circuit controls the most significant bit of the in-phase portion and the most significant bit of the orthogonal portion (n+2) bits of the output of the A/D converter for the in-phase and orthogonal portions.
1) A first circuit that calculates the exclusive inversion OR of the bit-th bit or the most significant bit of the orthogonal component and the exclusive inversion OR of the high-order (n+1) bit of the in-phase component; ) and the upper (n+2)th bit, and a second circuit that performs the AND of the respective results, and a third circuit that selects only the signal points that are the same distance from the in-phase axis and the orthogonal axis. The output of the circuit, the second circuit, and the third circuit are logically summed, and the result is logically ANDed with the timing signal to generate the first signal.
and a circuit for sampling and holding the output of the circuit.
The carrier wave regeneration circuit described in .