JPH0379904B2 - - Google Patents
Info
- Publication number
- JPH0379904B2 JPH0379904B2 JP56015775A JP1577581A JPH0379904B2 JP H0379904 B2 JPH0379904 B2 JP H0379904B2 JP 56015775 A JP56015775 A JP 56015775A JP 1577581 A JP1577581 A JP 1577581A JP H0379904 B2 JPH0379904 B2 JP H0379904B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- phase
- exclusive
- digital converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000008929 regeneration Effects 0.000 claims description 7
- 238000011069 regeneration method Methods 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims 2
- 238000011084 recovery Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000010355 oscillation Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101100488870 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) YPL062W gene Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】
本発明は、直交振幅変調信号より基準搬送波信
号を再生する搬送波再生回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a carrier regeneration circuit that regenerates a reference carrier signal from a quadrature amplitude modulation signal.
近年、高能率なデジタル搬送波伝送方式として
多値直交振幅変調方式の研究が進められている
が、その中の１つとして16QAM方式がある。こ
の方式を実現するうえで重要な回路として搬送波
再生回路があげられ、その故、従来種々の回路が
提案されている。その一つに特開昭50−28215号
公報「振幅位相変調信号復調装置」がある。 In recent years, research has been progressing on multilevel quadrature amplitude modulation methods as highly efficient digital carrier wave transmission methods, and one of them is the 16QAM method. A carrier wave regeneration circuit is an important circuit for realizing this method, and therefore various circuits have been proposed in the past. One of them is Japanese Patent Application Laid-Open No. 50-28215 entitled "Amplitude Phase Modulation Signal Demodulator".
この公報記載の技術を、第７図、第８図を参照
して説明する。第７図では16値QAM信号INが
AGC回路１でたとえば最大振幅値が一定となる
よう利得制御され、位相検波器２，３に入力され
る。位相検波器２，３にはVCO９の出力が供給
されるが、３にはπ／２移相器４が挿入されてい
るので、２，３は互いに直交位相関係にある。よ
つて、２，３の出力には入力信号が直交位相復調
された出力S1，S2が得られる。出力S1，S2は各々
５ビツトＡ／Ｄ変換器２１，２２に供給される。
Ａ／Ｄ変換器２１，２２の各５ビツト出力は論理
回路群２３に供給される。論理回路群２３は、供
給された10ビツトの信号にもとづいて、S1，S2が
所定の信号点に対して反時計回りに位相回転して
いるか、時計回りに位相回転しているかを判定
し、前者であれば“１”を、後者であれば“０”
を出力する。この論理回路群２３出力は低減濾波
器８で平滑化され、VCO制御信号として、VCO
９に供給され、VCO９の発振周波数が制御され
る。 The technique described in this publication will be explained with reference to FIGS. 7 and 8. In Figure 7, the 16-value QAM signal IN is
The gain is controlled by the AGC circuit 1 so that the maximum amplitude value is constant, for example, and is input to the phase detectors 2 and 3. The output of the VCO 9 is supplied to the phase detectors 2 and 3, and since the π/2 phase shifter 4 is inserted in the phase detector 3, the detectors 2 and 3 are in a quadrature phase relationship with each other. Therefore, outputs S 1 and S 2 obtained by quadrature phase demodulation of the input signals are obtained as outputs 2 and 3. The outputs S 1 and S 2 are supplied to 5-bit A/D converters 21 and 22, respectively.
Each 5-bit output of the A/D converters 21 and 22 is supplied to a logic circuit group 23. Based on the supplied 10-bit signal, the logic circuit group 23 determines whether S 1 and S 2 are phase-rotated counterclockwise or clockwise with respect to a predetermined signal point. If the former, set it as “1”, and if the latter, set it as “0”.
Output. The output of this logic circuit group 23 is smoothed by a reduction filter 8, and is used as a VCO control signal.
9, and the oscillation frequency of VCO 9 is controlled.
ここで第８図を参照し、論理回路群２３の入出
力論理を説明する。第８図において、白丸は16値
QAM信号の所定の信号点を、第１象限について
のみ示している。すなわち第８図はＡ／Ｄ変換器
２１，２２の最上位ビツトが共に“１”の場合の
論理回路群２３の入出力論理を示している。論理
回路群２３は、Ａ／Ｄ変換器２１，２２出力が、
第８図の領域A0，A1，B0，B1，C0，C1，D0，
D1のいずれにあるかを判定する。たとえば、領
域A1にある場合には、信号点S1，S2＝３，３が
反時計回りに位相回転しているとみなし、“１”
を出力し、領域A0にある場合には、信号点S1，
S2＝３，３が時計回りに位相回転しているとみな
し“０”を出力する。他の領域B0，B1，C0，C1，
D0，D1についても同様である。また他の象限に
ついても、同様な考え方で各領域及び各領域での
出力値が定められている。 Here, the input/output logic of the logic circuit group 23 will be explained with reference to FIG. In Figure 8, white circles represent 16 values.
Predetermined signal points of the QAM signal are shown only for the first quadrant. That is, FIG. 8 shows the input/output logic of the logic circuit group 23 when the most significant bits of the A/D converters 21 and 22 are both "1". In the logic circuit group 23, the outputs of the A/D converters 21 and 22 are
Areas A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 , in FIG.
Determine which of D 1 it is in. For example, if it is in area A 1 , signal points S 1 , S 2 = 3, 3 are considered to have phase rotation counterclockwise, and "1"
is output, and if it is in the area A 0 , the signal point S 1 ,
It is assumed that S 2 =3,3 is undergoing clockwise phase rotation and outputs "0". Other areas B 0 , B 1 , C 0 , C 1 ,
The same applies to D 0 and D 1 . Furthermore, for other quadrants, each region and the output value in each region are determined in a similar way.
領域A1，A0の境界は可能な限り直線的である
ことが好ましいため、Ａ／Ｄ変換器２１，２２は
S1，S2が各々４レベルであるにもかかわらず、５
ビツトの精度でＡ／Ｄ変換している。このため、
前記公報記載の技術ではＡ／Ｄ変換器２１，２２
としては入力信号のレベル数に比して多ビツトの
Ａ／Ｄ変換器が必要であり、またこれにともなつ
て論理回路群２３の内部構成も大規模となる。ま
た、以上の説明は16値QAMの場合であるが、32
値QAM、64値QAM、128値QAM、256値QAM
と信号点の数が増加するにしたがい、論理回路群
２３への入力ビツト数が増加するので、論理回路
群はさらに大規模化することがさけられない。 Since it is preferable that the boundaries between areas A 1 and A 0 be as straight as possible, the A/D converters 21 and 22
Although S 1 and S 2 are each at 4 levels, 5
A/D conversion is performed with bit precision. For this reason,
In the technique described in the above publication, A/D converters 21 and 22
Therefore, an A/D converter with a number of bits compared to the number of levels of the input signal is required, and the internal configuration of the logic circuit group 23 also becomes large-scale. Also, the above explanation is for 16-value QAM, but 32
Value QAM, 64 value QAM, 128 value QAM, 256 value QAM
As the number of signal points increases, the number of input bits to the logic circuit group 23 increases, so it is inevitable that the logic circuit group will become even larger.
本発明の目的は、上記欠点を除去し、非常に簡
略化された搬送波再生回路を提供することにあ
る。 The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a very simplified carrier recovery circuit.
以下図面を用いて詳細に説明する。 This will be explained in detail below using the drawings.
第１図は本発明による16QAM（Quadrature
Amplitude Moduration）用搬送波再生回路であ
り、１は入力信号INが入力される目動利得制御
回路（AGC回路）、２，３は位相検波器、４はπ/
２移相器、５，６は３ビツトのＡ／Ｄコンバータ、
７は排他的論理和（EX−OR）回路、８は低減
ろ波器（LPF）、９は電圧制御発振器（VCO）で
ある。第１図の回路において、VCO９の出力に
基準搬送波信号が再生される。 Figure 1 shows 16QAM (Quadrature) according to the present invention.
1 is a variable gain control circuit (AGC circuit) into which the input signal IN is input, 2 and 3 are phase detectors, and 4 is a π/
2 phase shifter, 5 and 6 are 3-bit A/D converters,
7 is an exclusive OR (EX-OR) circuit, 8 is a reduction filter (LPF), and 9 is a voltage controlled oscillator (VCO). In the circuit shown in FIG. 1, a reference carrier signal is reproduced at the output of the VCO 9.
以下動作を説明する。 The operation will be explained below.
入力信号INはAGC回路１にて出力レベルが一
定になるように制御され、次に、位相検波器２，
３に入力される、位相検波器２，３にはVCO９
の出力が供給されるが、３にはπ/2移相器４が挿
入されているので、２，３は互いに直交位相関係
にある。よつて、２，３の出力には入力信号が直
交位相復調された出力S1，S2が得られる。第２図
は16QAM信号を示しており、S1の信号は図中、
S1と示された軸上に投影された４値（±１、±３）
信号となる。又、S2信号は同様にS2軸に投影され
た４値信号となる。S1，S2信号は３ビツトＡ／Ｄ
コンバータ５，６に入り、ここで各々３ビツトの
２値デジタル信号X1〜X3，Y1〜Y3（以下添字数
字の小さなものを上位桁ビツトと呼ぶ）に変換さ
れる。ここで、X1〜X3，Y1〜Y3とS1，S2との間
の関係は第２図のように表わされ、これより明ら
かなように、X1，X2，Y1，Y2は16QAM信号の
主復調信号DATA１−１、DATA１−２、
DATA２−１、DATA２−２となる。また、
X3，Y3は16QAM信号の所定の信号位置からのず
れを示している。すなわち、Y3＝１のときは、
第２図の位相面上で、所定の信号位置から上にず
れていることを示し、Y3＝０のときは、下にず
れていることを示し、X3＝１のときは、所定の
信号位置から右にずれていることを示し、X3＝
０のときは左にずれていることを示している。 The input signal IN is controlled by the AGC circuit 1 so that the output level is constant, and then the phase detector 2,
VCO9 is input to phase detectors 2 and 3.
However, since a π/2 phase shifter 4 is inserted in 3, 2 and 3 are in a quadrature phase relationship with each other. Therefore, outputs S 1 and S 2 obtained by quadrature phase demodulation of the input signals are obtained as outputs 2 and 3. Figure 2 shows a 16QAM signal, and the S 1 signal is
4 values (±1, ±3) projected onto the axis labeled S 1
It becomes a signal. Similarly, the S 2 signal becomes a four-level signal projected onto the S 2 axis. S 1 and S 2 signals are 3-bit A/D
The signals enter converters 5 and 6, where they are converted into 3-bit binary digital signals X 1 to X 3 and Y 1 to Y 3 (hereinafter, the one with the smaller subscript number will be referred to as the upper digit bit). Here, the relationship between X 1 - X 3 , Y 1 - Y 3 and S 1 , S 2 is expressed as shown in Figure 2 , and as is clear from this , 1 , Y2 are the main demodulated signals DATA1-1, DATA1-2,
They become DATA2-1 and DATA2-2. Also,
X 3 and Y 3 indicate the deviation of the 16QAM signal from the predetermined signal position. That is, when Y 3 =1,
On the phase plane in Figure 2, it indicates an upward shift from the predetermined signal position, when Y 3 = 0 indicates a downward shift, and when X 3 = 1, it indicates a downward shift from the predetermined signal position. Indicates a shift to the right from the signal position, X 3 =
When it is 0, it indicates that it is shifted to the left.
ここで、基準搬送波信号とAGC回路１出力と
が、搬送波位相同期がとれておらず、第２図の矢
印方向に位相が回転している場合を考える。たと
えば（S1，S2）＝（３、３）の信号点が矢印方向に
回転した場合、X3＝０、Y1＝１となるので、EX
−OR回路７出力は１となる。また、（S1，S2）＝
（−３、−３）の信号点が矢印方向に回転すると、
X3＝１、Y1＝０となり、EX−OR回路７の出力
は１である。他の信号点についても同様であり、
搬送波非同期のために、位相検波器２及び３の出
力が反時計方向に位相回転している場合には、
EX−OR回路７の出力は１となる。 Here, let us consider a case where the reference carrier signal and the output of the AGC circuit 1 are not synchronized in carrier phase, and their phases are rotated in the direction of the arrow in FIG. For example, if the signal point (S 1 , S 2 ) = (3, 3) rotates in the direction of the arrow, X 3 = 0, Y 1 = 1, so EX
-OR circuit 7 output becomes 1. Also, (S 1 , S 2 )=
When the signal point (-3, -3) rotates in the direction of the arrow,
X 3 =1, Y 1 =0, and the output of the EX-OR circuit 7 is 1. The same goes for other signal points.
If the outputs of phase detectors 2 and 3 are rotated in phase in the counterclockwise direction due to carrier wave asynchronization,
The output of the EX-OR circuit 7 becomes 1.
一方、位相比較器２，３出力が時計方向に位相
回転している場合には、EX−OR回路出力は０
となる。また、AGC回路１出力がVCO９出力と
搬送波同期している場合には、EX−OR回路７
出力には１と０が各々50％の確率でランダムに生
起することは容易に理解できよう。 On the other hand, when the phase comparator 2 and 3 outputs are rotated clockwise, the EX-OR circuit output is 0.
becomes. Also, if the AGC circuit 1 output is carrier synchronized with the VCO 9 output, EX-OR circuit 7
It is easy to understand that 1 and 0 will each randomly occur in the output with a probability of 50%.
このEX−OR回路７出力は、低減濾波器８で
直流成分が抽出される。低減濾波器８出力は
VCO９に供給され、基準搬送波信号の周波数・
位相が制御される。すなわち、第２図の矢印方向
に位相検波器２，３出力が位相回転している場合
には、低減濾波器９から高いレベルの電圧が供給
されるため、この位相回転を補償すべく、VCO
９の発振周波数は高くなる。第２図の矢印と反対
方向に位相回転している場合には、低レベル電圧
が供給されるためVCO９の発振周波数は低くな
りこの位相回転が補償される。搬送波同期がとれ
ている場合には、中間レベルの電圧が低減濾波器
８から供給され、同期状態が保たれる。 A DC component of the output of this EX-OR circuit 7 is extracted by a reduction filter 8. Reduction filter 8 output is
The frequency and frequency of the reference carrier signal are supplied to VCO9.
Phase is controlled. In other words, when the outputs of the phase detectors 2 and 3 undergo a phase rotation in the direction of the arrow in FIG. 2, a high level voltage is supplied from the reduction filter 9.
The oscillation frequency of 9 becomes higher. When the phase rotation is in the opposite direction to the arrow in FIG. 2, the oscillation frequency of the VCO 9 is lowered and this phase rotation is compensated for since a low level voltage is supplied. When carrier synchronization is established, an intermediate level voltage is supplied from the reduction filter 8, and the synchronization state is maintained.
なお、第１図では、EX−OR回路７にX3とY1
とを入力しているが、その代りにX1とY3とを供
給してもよい。ただし、X1とY3との排他的論理
和は、第２図の矢印方向に位相回転しているとき
に０となり、矢印と反対方向に位相回転している
ときに１となる。このため、第１図のVCO回路
９のように電圧が高くなるほど発振周波数が高く
なる特性をもつ電圧制御発振器を用いる場合に
は、EX−OR回路７出力を否定回路で反転して
から、低減濾波器８に供給する必要がある。ま
た、AGC回路１はＡ／Ｄコンバータ５，６の入
力点のレベルが一定になるように動作させた方が
２，３の利得変動をも救済できるので望ましい。 In addition, in Fig. 1, X 3 and Y 1 are connected to the EX-OR circuit 7.
is input, but X 1 and Y 3 may be supplied instead. However, the exclusive OR of X 1 and Y 3 becomes 0 when the phase is rotated in the direction of the arrow in FIG. 2, and becomes 1 when the phase is rotated in the opposite direction to the arrow. Therefore, when using a voltage controlled oscillator that has the characteristic that the oscillation frequency increases as the voltage increases, such as the VCO circuit 9 in Figure 1, the output of the EX-OR circuit 7 is inverted with an inverting circuit, and then the output is reduced. It is necessary to supply it to the filter 8. Further, it is preferable that the AGC circuit 1 is operated so that the levels at the input points of the A/D converters 5 and 6 are constant, since this can also relieve a few gain fluctuations.
第３図は16QAM搬送波再生回路の他の実施例
であり、１０はEX−OR回路、１１はLPF、１
２は減算器である。第３図は第１図に１０〜１２
を追加したものであり、１０の出力すでに述べた
とおり、矢印の方向の位相回転の時の信号、逆の
時は１の信号が生ずる。即ち７の出力と逆極性の
制御信号を生ずる。よつて７及び１０の出力を８
及び１１を介して減算器１２で減算し、その出力
でVCO９を制御すれば、第３図も第１図と同様
に動作する。 Figure 3 shows another embodiment of the 16QAM carrier recovery circuit, in which 10 is an EX-OR circuit, 11 is an LPF, 1
2 is a subtractor. Figure 3 is 10 to 12 in Figure 1.
As mentioned above, a signal of 1 is generated when the phase is rotated in the direction of the arrow, and a signal of 1 is generated when the phase is rotated in the opposite direction. That is, a control signal having a polarity opposite to that of the output of 7 is generated. Therefore, the output of 7 and 10 is 8
If subtractor 12 performs subtraction through subtractor 11 and 11, and the VCO 9 is controlled by the output, FIG. 3 operates in the same manner as FIG. 1.
第１図に比して第３図の利点は制御信号に含ま
れるジツタ成分を約3dB抑圧できる点にある。何
故ならば、７及び１０の出力は各々独立に再生さ
れているので、それらに含まれるジツタ成分は互
いに無相関であるが、信号成分は極性は逆ながら
互いに同期しているからである。 The advantage of FIG. 3 over FIG. 1 is that the jitter component included in the control signal can be suppressed by about 3 dB. This is because the outputs 7 and 10 are each reproduced independently, so the jitter components contained therein are uncorrelated with each other, but the signal components are synchronized with each other although their polarities are opposite.
第３図でLPFと減算器の位置を逆にしても同
様な効果を得ることができる。即ち７，１０の出
力を減算器１２にて減算し、その出力をLPE８
を介してVCO９に入力する構成である。 A similar effect can be obtained by reversing the positions of the LPF and subtractor in FIG. That is, the outputs of 7 and 10 are subtracted by the subtracter 12, and the output is sent to the LPE8.
The configuration is such that the signal is input to the VCO 9 via the .
第４図は64QAM用搬送波再生回路の実施例で
あり、１３，１４は４ビツトのＡ／Ｄコンバータ
である。動作は第３図の場合と基本的には同様で
あり、Ａ／Ｄコンバータ１３，１４の上位ビツト
X1〜X3，Y1〜Y3は64QAM信号の主復調信号
DATA１−１、DATA１−２、DATA１−３、
DATA２−１、DATA２−２、DATA２−３と
なる。又最下位ビツトX4，Y4は64QAM信号の64
点の信号位置のずれを検出し、１又は０を出力
し、X1，Y1は64点の信号が位置する象限を判定
し、１又は０を出力する。よつてX4とY1をEX−
OR７で、Y4とX1をEX−OR回路１０にてEX−
OR操作すれば、７，１０の出力に、復調信号
S1，S2が受けている位相回転を検出できる、互い
に逆極性の制御信号を得ることができるので、そ
れら出力をジツタ成分抑圧用のLPF８及び１１
を介して、減算器１２にて減算し、その出力にて
VCO９を制御すれば本回路は動作する。 FIG. 4 shows an embodiment of a carrier wave recovery circuit for 64QAM, and 13 and 14 are 4-bit A/D converters. The operation is basically the same as that shown in FIG. 3, and the upper bits of A/D converters 13 and 14
X 1 to X 3 , Y 1 to Y 3 are the main demodulated signals of the 64QAM signal
DATA1-1, DATA1-2, DATA1-3,
They become DATA2-1, DATA2-2, and DATA2-3. Also, the least significant bits X 4 and Y 4 are 64 of the 64QAM signal.
Detects a shift in the signal position of a point and outputs 1 or 0. X 1 and Y 1 determine the quadrant in which the 64-point signal is located and outputs 1 or 0. Therefore, X 4 and Y 1 are EX−
With OR7, Y 4 and X 1 are EX-OR circuit 10 with EX-
If you perform OR operation, the demodulated signal will be output as 7 and 10.
Since it is possible to obtain control signals with opposite polarities that can detect the phase rotation that S 1 and S 2 receive, their outputs are passed to LPFs 8 and 11 for jitter component suppression.
subtracter 12, and its output is
This circuit operates if VCO9 is controlled.
第４図では、互いに逆相関係にある７及び１０
の出力を両者とも使用する回路構成となつている
が、第１図に示されている如く、どちらか一方の
みでも動作させることができるのは明らかであ
る。 In Figure 4, 7 and 10 are in an antiphase relationship with each other.
Although the circuit configuration is such that both outputs are used, it is clear that it can be operated using only one of them, as shown in FIG.
以上多値QAM方式に対する本発明の適用性に
ついて述べたが、4QAM即ち4PSK方式に対して
も本発明は適用可能である。第５図、第６図は
4PSK用搬送波再生回路であり、１５，１６は２
ビツトのＡ／Ｄコンバータであり、その他の構成
ユニツトは第１，３，４図にて用いられたものと
全く同一である。動作においても、第１，３，４
図との相違はＡ／Ｄコンバータのみであり、上位
ビツトX1，Y1が主復調信号DATA１−１、
DATA２−１で且つ象限判定信号、下位ビツト
X2，Y2が信号点の位置ずれ信号として用いられ
る。 Although the applicability of the present invention to the multilevel QAM method has been described above, the present invention is also applicable to 4QAM, that is, 4PSK method. Figures 5 and 6 are
This is a carrier wave regeneration circuit for 4PSK, and 15 and 16 are 2
The other components are exactly the same as those used in FIGS. 1, 3, and 4. In operation, the 1st, 3rd, and 4th
The only difference from the figure is the A/D converter, and the upper bits X1 , Y1 are the main demodulated signals DATA1-1,
DATA2-1 and quadrant judgment signal, lower bit
X 2 and Y 2 are used as signal point position deviation signals.
以上、本発明による4QAM（4PSK）、16QAM、
64QAM用搬送波再生回路について述べたが、そ
れらを構成するうえでの相違点は単にＡ／Ｄコン
バータのビツト数のみであり、本発明によれば、
非常に簡略化されたQAM用搬送波再生回路を実
現できる。すなわち、本願は4QAM、16QAM、
32QAM、64QAM、…、256QAM…と信号点の
数を増加させた場合でも、Ａ／Ｄ変換器５，６の
ビツト数をそれに応じて増加させるだけでよいの
で、特開昭50−28215号公報記載の従来技術のよ
うに信号点増加による装置規模の増大を抑制でき
る。本発明による搬送波再生回路の主構成ユニツ
トはＡ／Ｄコンバータであり、この性能によつて
本回路のそれが左右されるが、最近ではLSI技術
がめざましく進歩し、高速、高分解能等の高性能
なＡ／Ｄコンバータが開発、市販されるようにな
り、今後ますます加速度的に進歩すると思われ
る。そうなれば、本発明による効果はますます大
きくなる。 As described above, 4QAM (4PSK), 16QAM, and
Although the carrier wave recovery circuit for 64QAM has been described, the only difference in configuring them is the number of bits of the A/D converter, and according to the present invention,
A very simplified carrier wave recovery circuit for QAM can be realized. In other words, this application applies to 4QAM, 16QAM,
Even if the number of signal points is increased to 32QAM, 64QAM, ..., 256QAM, etc., it is only necessary to increase the number of bits of the A/D converters 5 and 6 accordingly. It is possible to suppress an increase in the scale of the device due to an increase in signal points as in the prior art described above. The main constituent unit of the carrier regeneration circuit according to the present invention is the A/D converter, and the performance of this circuit is influenced by the performance of the A/D converter.Recently, LSI technology has made remarkable progress, and high performance such as high speed and high resolution has been achieved. A/D converters have been developed and are now on the market, and progress is expected to continue at an accelerating pace in the future. If this happens, the effects of the present invention will become even greater.
第１図は本発明による16QAM搬送波再生回路
を示すブロツク図、第２図は16QAM変調信号を
説明するための図、第３図は本発明による他の
16QAM搬送波再生回路を示すブロツク図、第４
図は本発明による64QAM搬送波再生回路を示す
ブロツク図、第５図は本発明による4PSK搬送再
生回路を示すブロツク図、第６図は本発明による
他の4PSK搬送波再生回路を示すブロツク図、第
７図は従来技術の一例を示すブロツク図、第８図
は従来技術の動作を説明するための図である。
１は自動利得制御回路、２，３は位相検波器、
４はπ／２移相器、５，６，１３，１４，１５及
び１６はアナログ−デジタル変換器、７，１０は
EX−OR回路、８，１１は低減ろ波器、１２は
減算器である。
FIG. 1 is a block diagram showing a 16QAM carrier recovery circuit according to the present invention, FIG. 2 is a diagram for explaining a 16QAM modulated signal, and FIG.
Block diagram showing the 16QAM carrier recovery circuit, No. 4
FIG. 5 is a block diagram showing a 64QAM carrier recovery circuit according to the present invention, FIG. 5 is a block diagram showing a 4PSK carrier recovery circuit according to the invention, FIG. 6 is a block diagram showing another 4PSK carrier recovery circuit according to the invention, and FIG. The figure is a block diagram showing an example of the prior art, and FIG. 8 is a diagram for explaining the operation of the prior art. 1 is an automatic gain control circuit, 2 and 3 are phase detectors,
4 is a π/2 phase shifter, 5, 6, 13, 14, 15 and 16 are analog-to-digital converters, and 7, 10 are
EX-OR circuit, 8 and 11 are reduction filters, and 12 is a subtracter.
Claims (1)
幅変調信号より基準搬送波信号を再生する搬送波
再生回路であり、制御信号により周波数が変化す
る前記基準搬送波を生成する電圧制御発振器と、
該電圧制御発振器の出力を用いて上記直交振幅変
調信号を直交位相検波し２つのベースバンド信号
を出力する位相検波器と、 前記２つのベースバンド信号の一方を少なくと
も（ｍ＋１）ビツト（ｍ＝log2N、ただし小数値
は切上げる）のデイジタル信号に変換出力する第
１のアナログ−デイジタル変換器と、 前記第２つのベースバンド信号の他方を少なく
とも（ｍ＋１）ビツトのデイジタル信号に変換出
力する第２のアナログデイジタル変換器と、 前記第１のアナログ−デイジタル変換器の最上
位ビツト出力と前記第２のアナログ−デイジタル
変換器の最上位から（ｍ＋１）番目のビツトとの
排他的論理和をとり、この排他的論理和結果より
前記制御信号を得る手段 とから構成されることを特徴とする搬送波再生回
路。 ２ 同相信号、直交成分が各々Ｎ値である直交振
幅変調信号より基準搬送波信号を再生する搬送波
再生回路であり、 制御信号により周波数が変化する前記基準搬送
波を生成する電圧制御発振器と、 該電圧制御発振器の出力を用いて上記直交振幅
変調信号を直交位相検波し２つのベースバンド信
号を出力する位相検波器と、 前記２つのベースバンド信号の一方を少なくと
も（ｍ＋１）ビツト（ｍ＝log2N、ただし小数値
は切あげる）のデイジタル信号に変換出力する第
１のアナログ−デイジタル変換器と、 前記２つのベースバンド信号の他方を少なくと
も（ｍ＋１）ビツトのデイジタル信号に変換出力
する第２のアナログデイジタル変換器と、 前記第１のアナログ−デイジタル変換器の最上
位ビツト出力と前記第２のアナログ−デイジタル
変換器の最上位から（ｍ＋１）番目のビツトとの
排他的論理和をとる第１の排他的論理和手段と、 前記第２のアナログ−デイジタル変換器の最上
位ビツト出力と前記第１のアナログ−デイジタル
変換器の最上位から（ｍ＋１）番目のビツトとの
排他的論理和をとる第２の排他的論理和手段と、 前記第１の排他的論理和手段出力と前記第２の
排他的論理和手段出力との差信号にもとづいて前
記制御信号を生成する手段、 とから構成されることを特徴とする搬送波再生回
路。[Claims] 1. A carrier regeneration circuit that regenerates a reference carrier signal from a quadrature amplitude modulation signal in which in-phase components and quadrature components each have N values, and voltage control that generates the reference carrier wave whose frequency changes according to a control signal. an oscillator;
a phase detector that performs quadrature phase detection of the quadrature amplitude modulation signal using the output of the voltage controlled oscillator and outputs two baseband signals; a first analog-to-digital converter that converts and outputs the other of the second baseband signals into a digital signal of at least (m+1) bits; taking the exclusive OR of the most significant bit output of the first analog-to-digital converter and the (m+1)th most significant bit from the most significant bit of the second analog-to-digital converter; and means for obtaining the control signal from the exclusive OR result. 2. A carrier wave regeneration circuit that regenerates a reference carrier wave signal from a quadrature amplitude modulation signal in which an in-phase signal and a quadrature component each have an N value, and a voltage controlled oscillator that generates the reference carrier wave whose frequency changes according to a control signal; a phase detector that performs quadrature phase detection of the quadrature amplitude modulation signal using the output of the controlled oscillator and outputs two baseband signals; a first analog-to-digital converter that converts and outputs the other of the two baseband signals into a digital signal of at least (m+1) bits; a digital converter; an exclusive OR means, a first one for calculating an exclusive OR of the most significant bit output of the second analog-to-digital converter and the (m+1)th most significant bit from the most significant bit of the first analog-to-digital converter; 2 exclusive OR means; and means for generating the control signal based on a difference signal between the output of the first exclusive OR means and the output of the second exclusive OR means. A carrier wave regeneration circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56015775A JPS57131151A (en) | 1981-02-06 | 1981-02-06 | Carrier wave reproducing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56015775A JPS57131151A (en) | 1981-02-06 | 1981-02-06 | Carrier wave reproducing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57131151A JPS57131151A (en) | 1982-08-13 |
| JPH0379904B2 true JPH0379904B2 (en) | 1991-12-20 |
Family
ID=11898182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56015775A Granted JPS57131151A (en) | 1981-02-06 | 1981-02-06 | Carrier wave reproducing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57131151A (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939149A (en) * | 1982-08-28 | 1984-03-03 | Nec Corp | Multi-value orthogonal amplitude demodulator |
| JPS5980048A (en) * | 1982-10-30 | 1984-05-09 | Nec Corp | Automatic phase control circuit |
| JPS59161149A (en) * | 1983-03-04 | 1984-09-11 | Nec Corp | Timing synchronizing circuit |
| JPS6156555A (en) * | 1984-08-27 | 1986-03-22 | Nec Corp | Demodulator |
| US4703282A (en) | 1985-06-29 | 1987-10-27 | Nec Corporation | Digital demodulation system |
| JPS6210950A (en) * | 1985-07-08 | 1987-01-19 | Nec Corp | Digital radio communication system |
| US4726043A (en) * | 1986-11-28 | 1988-02-16 | American Telephone And Telegraph Company | Data decision-directed timing and carrier recovery circuits |
| JPS63310252A (en) * | 1987-06-12 | 1988-12-19 | Fujitsu Ltd | Carrier wave regenerating circuit |
| JP2513318B2 (en) * | 1989-06-30 | 1996-07-03 | 日本電気株式会社 | Carrier wave regeneration circuit |
| US5134634A (en) * | 1989-08-31 | 1992-07-28 | Nec Corporation | Multilevel quadrature amplitude demodulator capable of compensating for a quadrature phase deviation of a carrier signal pair |
| JP2540982B2 (en) * | 1990-04-26 | 1996-10-09 | 日本電気株式会社 | Digital demodulator |
| JP2771365B2 (en) * | 1991-09-30 | 1998-07-02 | 福島日本電気株式会社 | Carrier recovery circuit |
| JP3794412B2 (en) | 2002-03-11 | 2006-07-05 | 松下電器産業株式会社 | Carrier recovery device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55134563A (en) * | 1979-04-05 | 1980-10-20 | Nec Corp | Offset qpsk phase difference detector |
-
1981
- 1981-02-06 JP JP56015775A patent/JPS57131151A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55134563A (en) * | 1979-04-05 | 1980-10-20 | Nec Corp | Offset qpsk phase difference detector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57131151A (en) | 1982-08-13 |
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