JP2540958B2 - Digital modulation / demodulation system - Google Patents

Description

The present invention relates to a digital modulation / demodulation system for compositely transmitting a sub data signal by using phase modulation on a main data line using quadrature amplitude modulation.

[Prior Art] Quadrature amplitude modulation has become the mainstream of carrier wave digital transmission systems in recent years because of its high efficiency.

A digital modulation / demodulation system has been proposed in which the quadrature amplitude modulation wave modulated by the main data signal is 2α radian phase modulated by the sub data signal in order to efficiently perform composite transmission of the sub data signal on the main data line using quadrature amplitude modulation. (Japanese Patent Application No. 61-24950).

Here, the above digital modulation / demodulation system will be described.

FIG. 6 (a) is a signal arrangement diagram of a composite modulation wave obtained by modulating a 16-value quadrature amplitude modulation wave by ± α radian phase.

16 signal points C _ij (i, j are 1 to 1) corresponding to the main data signal
4) is converted to the signal point A _ij or B _ij by the phase modulation of ± α radian by the sub data signal.

A composite modulated wave whose signal point is A _ij or B _ij is reproduced as a main data signal and a sub data signal as described below.

First, quadrature phase detection is performed on the composite modulated wave to obtain demodulation outputs P ₀ and Q ₀ that are orthogonal projections of the signal point A _ij or B _{ij on} the P and Q axes.

The sub-data signal can be reproduced by logically operating the data obtained by multi-level discrimination of the demodulation outputs P ₀ , Q ₀ with the discrimination levels of ± L, ± 3L and the data obtained by discrimination with the discrimination level of 0. . In addition, demodulation outputs P ₀ and Q ₀ are obtained by using the circuits shown in FIGS. 7 and 9 shown in Japanese Patent Publication No. 58-698 “Phase synchronization circuit”.
It is also possible to reproduce the sub data signal from the.

The demodulated outputs P ₀ and Q ₀ are multivalued through the + α radian phase shifter and −α radian phase shifter, which are analog operation circuits, and either of the obtained output data is converted into the previously obtained sub data signal. The main data signal can be reproduced by corresponding selection.

Since the discrimination margin of the sub-data signal is smaller than that of the main data signal, if the code transmission rates of both data signals are the same, the code error rate characteristic of the sub-data signal deteriorates and the signal error of the sub-data signal causes the main error. Since the reproduction of the data signal is also erroneous, the code transmission speed of the sub data signal is set to be an integer (m) of the code transmission speed of the main data signal, and the sub data signal is improved by the band limitation or the majority decision. It is necessary to sufficiently improve the bit error rate characteristic of. Also, the larger the value of α, the better the bit error rate characteristic of the sub-data signal, but on the contrary, the worse the bit error rate characteristic of the main data signal, so there is a limit to that value. 0.
It is about 16 radians. In this case, although it depends on the signal point, the C / N deterioration amount is about 6 dB with respect to the main data signal at the best point. In the case of 16 values, it is possible to reduce the value of m to about 8.

[Problems to be Solved by the Invention] With the above-described conventional digital modulation / demodulation system, by appropriately selecting the values of α and m, the sub data signal can be generated without degrading the code error rate of the main data signal. Can be transmitted.

However, in this system, the amount of phase modulation due to the sub-data signal is constant as α radian regardless of the amplitude value of the modulated wave due to the main data signal, and therefore the C / N value of the sub-data signal reproduced on the demodulation side is It greatly depends on the modulation amplitude value of the main data signal.

Referring to FIG. 6 (a), the signal level of the sub data signal when the modulation amplitude value of the main data signal is maximum is A ₁₁ B ₁₁ , and when it is minimum, it is A ₁₄ B ₁₄ . In this way, there is a difference of about 9 dB between the two, and the bit error rate characteristic of the sub data signal is determined by the worst value A ₁₄ B ₁₄ , and the amount of information in the sub data signal cannot be increased. In other words, the conventional digital modulation / demodulation system is not efficient.

An object of the present invention is to provide a digital modulation / demodulation system capable of changing the modulation phase amount of a sub data signal according to the modulation amplitude value of the main data signal and further improving the code error rate characteristic of the sub data signal. is there.

[Means for Solving Problems] In the digital modulation / demodulation system of the present invention, the modulator transmits a quadrature amplitude modulated wave modulated by a main data signal having a code transmission rate f ₁ to a code transmission rate f ₂ (f ₁ > f _2). ) Is provided with means for obtaining a composite modulated wave by phase-modulating at least one of two values of 2α radian and 2β radian according to the amplitude value of the quadrature amplitude modulated wave. And a demodulation device that obtains first and second demodulation signals by quadrature phase detection of the composite modulation wave, and multi-valued discrimination of the demodulation signal to calculate a data signal, and the sub-data. Means for reproducing a signal, level discriminating means for receiving the data signal to discriminate the amplitude value of the composite modulated wave and outputting a discriminating signal, and receiving the data signal in response to the sub data signal and the discriminating signal. At least the above α and 2β
Main data signal reproducing means for controlling the phase of radians and reproducing the main data signal.

[Examples] Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 (a) is a block diagram showing an embodiment of the modulation device according to the present invention, showing the case where the main data signal is 16QAM, so that the modulation signal device shown in FIG. 6 (b) can be obtained. Is composed of.

In FIG. 6 (b), when the amplitude value of the main data signal is between maximum and intermediate (maximum; A _i1 B _i1 , intermediate; A _i2 B _i2 , A _i3 B _i3 , where i
1 to 4), the amount of phase modulation by the sub data signal is 2α radians, and when the amplitude value of the main data signal is minimum (minimum; A _i4 B _i4 ), the amount of phase modulation by the sub data signal is 2 β.
It is set to radians (β> α). Here, when the main data signal is 16QAM, the value of β can be set up to about twice the value of α.

Referring to FIG. 1 (b), main data signals (X1,2 and Y
1,2) and the sub data signal (D) are input to the ROMs 15 and 16,
Here, a multi-bit binary signal obtained by orthogonally projecting the signal arrangement of FIG. 6 (b) to the P axis and the Q axis is created, and then the D / A converters 17 and 1 are used.
Converted to an analog quantity by 8. D / A converters 17 and 18
Is output to the quadrature modulator composed of the multipliers 21 and 22 and the π / 2 transfer unit 23 via the low-pass filters (LPF) 19 and 20, respectively. Then, the intermediate frequency (IF) signal of the local oscillator 24 is subjected to quadrature modulation here. As a result, the modulation signal arrangement shown in FIG. 6 (b) is obtained as an output.

Here, referring to FIG. 1 (a), the demodulator used in the present invention comprises an intermediate frequency amplifier 1 for amplifying an input signal IN.
, A voltage controlled oscillator (hereinafter referred to as VCO) 2, a quadrature phase detector 3 which inputs the amplified output of the intermediate frequency amplifier 1 and the oscillation output of VCO 2 and outputs demodulated outputs P ₀ and Q ₀ , and the demodulated output P respectively. Baseband amplifiers 4 and 5 for amplifying ₀ and Q _0, and analog / digital converters (hereinafter referred to as AD converters) that input the amplified outputs of the baseband amplifiers 4 and 5 and output demodulated data D _p and D _q , respectively. 6, 7 and the demodulated data D _p and D _q and the sub data signal reproduction circuit 8 that outputs the sub data signal S, and the demodulated data D _p and D _q to the sub data signal reproduction circuit 8
Of the delay circuit 13, the level discriminating circuit 14 for inputting the output of the delay circuit 13 to discriminate the amplitude value of the main data signal, the output of the delay circuit 14, the discriminating signal H and the sub data signal S. A main data signal reproduction circuit 9 for outputting main data signals X1, X2, Y1, Y2 and data signals X3, Y3,
Input data signals X3 and Y3 and input the signal to baseband amplifier 4,5
Low pass filter (hereinafter referred to as LPF) 10 to be output to and a logic circuit to input data signals X1, X3, Y1 and Y3, respectively.
It has 11,12 and. The logic circuit 11 is an intermediate frequency amplifier 1,
The signal is output to the baseband amplifier 5, and the logic circuit 12 outputs VC
Output signal to O2.

This demodulator is an example of using 16-valued quadrature amplitude modulation as the modulation method of the main data signal, and the input signal IN is a 16-valued quadrature amplitude modulated wave () obtained by modulating the main data signals X1, X2, Y1 and Y2. (The normal position of the signal point is C _ij in FIG. 6 (b)). The sub-data signal S has the maximum amplitude value of the 16-valued quadrature amplitude modulation wave, ± α radian in the middle, and the minimum amplitude value. In this case, it is a composite modulated wave in the intermediate frequency band that is ± β radian phase modulated, and its signal points are A _ij and B _ij in FIG. 6 (b). Of the main data signals, X1 and X2 determine the position of the signal point C _{ij in} the P-axis direction, and Y1 and Y2 determine the position of the Q-axis direction. In addition, the main data signal that determines the quadrant of the signal point is X1, Y
Suppose it is 1. The code transmission rate of the sub data signal is set to 1 / m of the code transmission rate of the main data signal.

The input signal IN is amplified to a predetermined amplitude by the intermediate frequency amplifier 1 and quadrature detected by the quadrature detector 3 with the VCO2 output as a reference phase. A detection output demodulated output P _0, Q ₀ is the orthogonal projection of the signal point Aij or B _ij P, the Q-axis.

The demodulation outputs P ₀ and Q ₀ are the respective baseband amplifiers 4,5 and
Is amplified with a predetermined amplitude at, multi-valued is discriminated by the AD converters 6 and 7, and is converted into demodulated data D _p and D _q . The greater the number of bits of the demodulated data D _p and D _q, the better the accuracy of the signal processing thereafter, but in the case of 16 values, about 8 bits are sufficient.

The sub-data signal reproducing circuit 8 is composed of a logic circuit and a digital arithmetic circuit, as will be described later. The logic circuit outputs coefficient data corresponding to the demodulated data D _p and D _q . The digital operation circuit digitally operates the coefficient data and the demodulated data D _p and D _q to reproduce the sub data signal S.

The main data signal reproduction circuit 9 also includes a logic circuit and a digital arithmetic circuit, as will be described later.
The coefficient data is output corresponding to the sub data signal S output from the sub data signal reproducing circuit 8. The digital arithmetic circuit is
The coefficient data and the demodulated data D _p , D _q are digitally calculated to obtain the sub data signal S from the demodulated data D _p , D _q.
The phase modulation component due to is removed. The most significant bit and the second most significant bit of the two data thus obtained are
The main data signals are X1, Y1 and X2, Y2. The third most significant bit is the data signal X3, Y3.

Since the data signals X3 and Y3 represent the deviations of the input signals of the AD converters 6 and 7 from the normal values, the data signal X3 is set to LPF1.
By controlling the output DC level of the baseband amplifier 4 with the output reduced and filtered by 0, and the output DC level of the baseband amplifier 5 by the output obtained by reducing and filtering the data signal Y3 with LPF10, A-D The drift of the DC component of the input signals of the converters 6 and 7 can be compensated. The operation of this DC drift compensation is described in detail in the "demodulator" by the present inventor (Japanese Patent Laid-Open No. 58-101449).

The logic circuit 11 controls the gains of the intermediate frequency amplifier 1 and the baseband amplifier 5 with the two signals obtained from the data signals X1, X3, Y1 and Y3, so that the input signal amplitudes of the AD converters 6 and 7 are controlled. Is a circuit for maintaining a normal value, and its configuration and operation are described in detail in "Automatic Gain Control Circuit" (Japanese Patent Laid-Open No. 59-169256) by the present inventor.

The logic circuit 12 is a circuit that forms a phase locked loop by controlling VCO2 with the signals obtained from the data signals X1, X3, Y1 and Y3. Regarding the configuration and operation, the "carrier recovery circuit" by the present inventor is used. (Japanese Patent Application Laid-Open No. 57-131151).

FIGS. 2A and 2B are block diagrams showing two configuration examples of the sub data signal reproducing circuit 8.

The sub-data signal reproducing circuit 8 shown in FIG. 2 (a) includes a logic circuit 81 which inputs demodulated data D _p and D _q and outputs coefficient data M _p1 and M _q1 , and demodulated data D _p and D _q and coefficients, respectively. Multipliers 82 and 83 to which the data M _p1 and M _q1 are input, a subtracter 84 that subtracts the output of the multiplier 83 from the output of the multiplier 82, and a subtractor 84
And a majority decision circuit 85 for receiving the output of the sub-data signal S and outputting the sub-data signal S.

The logic circuit 81 determines the position (value of i, j) of the signal point C _ij from the upper 2 bits of the demodulated data D _p and D _q corresponding to the main data signals X1, X2 and Y1, Y2, and the determination result And outputs coefficient data M _p1 and M _q1 .

This correspondence is shown in FIGS. 3 (a) and 3 (b). FIG. 3A is an explanatory diagram showing the correspondence between the signal points C _ij and the absolute values of the coefficient data M _p1 and M _q1 . Figure 3 (b) shows the signal points
It is explanatory drawing which shows the correspondence of C _ij and the polarities of coefficient data M _p1 and M _q1 .

When the signal point C _ij is in the first quadrant or the third quadrant (i
Is 1 or 3, j is 1 to 4), the multipliers 82 and 83 are signal points
Demodulated data D _p , D _q corresponding to A _ij are converted into data corresponding to signal point A ₁₁ and demodulated data D _ij corresponding to signal point B _ij
Convert _p and D _q into data corresponding to the vicinity of signal point B ₁₁ . As a result, the data string output by the subtractor 84 equivalently represents the analog amount of the sub-data signal S, the most significant bit of which is positive when the signal point is A _ij and is the signal point B _ij . At some point, the data will be negative. When the signal point C _ij is in the second or fourth quadrant (i is 2 or 4, j
Is 1 to 4), the multipliers 82 and 83 are the signal points A _ij or B.
_Since the demodulated data D _p , D _q corresponding to _ij are converted into data corresponding to the vicinity of the signal point B ₃₁ or the vicinity of the signal point A ₃₁ , in this case as well, the most significant bit of the data string output by the subtractor 84 is
The data indicates that the signal points are positive when A _ij and negative when B _ij . Therefore, by checking whether the most significant bit of the data string output from the subtractor 84 is positive or negative, it can be determined whether the signal point is A _ij or B _ij . In other words, the sub data signal S is can get.

Since the data string output speed of the subtractor 84 is equal to the code transmission speed of the main data signal, the subtractor 84 outputs the data string m times for one code of the sub data signal S. Majority decision circuit 85
Outputs the judgment result as a sub data signal S for a period of m times by counting the most significant bits of the output of the subtractor 84 m times and making a majority decision. This majority logic operation improves the code error rate characteristic of the sub data signal S.

The sub data signal reproducing circuit 8 shown in FIG.
It is configured by removing the majority decision circuit 85 from the sub data signal reproduction circuit 8 shown in FIG. 9A and adding a DA converter 86, an LPF 87, and an AD converter 88.

The data string output by the subtractor 84 is converted into an analog value by the DA converter 86, band-limited by the LPF 87, and 1-bit A-
It is digitized by the D converter 88 and becomes the sub data signal S. Due to the band limitation of the LPF 87, the code error rate characteristic of the sub data signal S is improved. The band of LPF87 is set near 1 / m of the code transmission rate of the main data signal.

FIG. 4 is a block diagram showing the main data signal reproducing circuit 9.

The main data signal reproducing circuit 9 shown in FIG. 4 receives the sub data signal S and outputs the coefficient data M _p2 and M _q2.
2, a multiplier for inputting demodulated data D _q and coefficient data M _p2
93, a multiplier 94 that inputs the demodulated data D _p and the coefficient data M _q2 , an adder 95 that inputs the demodulated data D _p and the output data of the multiplier 93, and outputs data signals X1 to X3, The demodulated data D _q and the output data of the multiplier 94 are input, and the data signal Y1
And an adder 96 that outputs Y3.

The delay circuit 13 provided at the input of the main data signal reproducing circuit 9 delays the demodulated data D _p and D _q . This delay time is from the input of the first demodulated data D _p , D _q used to obtain one code of the sub data signal S to the sub data signal reproduction circuit 8 to the beginning of the code of the sub data signal S. Set to the time. By this setting, the demodulated data D _p and D _q used to obtain one code of the sub data signal S while the one code of the sub data signal S is being inputted to the main data signal reproducing circuit 9 are multiplied by the multipliers 93, 94 and the adder 95, Enter in 96.

The logic circuit 92 outputs coefficient data M _p2 and M _q2 having the relationship shown in FIG. 5 according to the sub data signal S and the level determination signal H. In the figure, the amplitude value of the main data signal is maximum when the H signal is 1, and is minimum when the H signal is O.

The digital operation by the multipliers 93, 94 and the adders ₉₅ , ₉₆ is expressed as the addition result data D ₉₅ , D ₉₆ of the adders ₉₅ , _96, and can be written as follows when the H signal is 1.

However, if the value of the sub data signal S is the signal point A _{i (1 to 3)}
Corresponding to the positive and negative signs on the upper side, signal point B _{i (1 to 3)}
When it corresponds to, the lower sign is taken.

In the equation (1), when the coefficient (1 / cosα) having a constant value is ignored, the vector (D _p , D _q ) corresponding to the signal point A _{i (1 to 3)} or B _{i (1} to ₃₎ is expressed by α. Since the formula is such that radians or −α radians are rotated, even if the demodulated data D _p and D _q are data corresponding to the signal points A _{i (1} to _3), they correspond to the signal points B _{i (1} to ₃₎ . Data D
₉₅ and D ₉₆ are data corresponding to the signal points C _{i (1} to ₃₎ . The same applies when the H signal is O (the main signal is the minimum),
Since the main data signal reproducing circuit 9 rotates the vector (D _p , D _q ) corresponding to the signal point A _i4 or B _i4 by β radians or −β radians, the demodulated data D _p , D _q corresponds to the signal point A _i4 . be data corresponding to the signal point B _i4 be the data, the data D _95, D ₉₆ is the data corresponding to the signal point C _i4. Therefore, the data D ₉₅ and D ₉₆ are data obtained by removing the phase modulation component of the sub data signal S from the demodulated data D _p and D _q .

The adders ₉₅ and ₉₆ output the upper 3 bits of the addition result data D ₉₅ and D ₉₆ , respectively, as data signals X1 to X3 and Y1 to Y3.

As described above, according to the present invention, when the amplitude value of the main data signal is minimum, the modulation phase amount of the sub data signal can be set to 2β radian, which is about 20 log (s).
In β / sin α) C / N ratio can be improved and the bit error rate characteristic of the sub data signal can be improved. In other words, there is an advantage that the code rate ratio m between the main signal and the sub signal can be reduced.

It should be noted that if the ratio of α to β is made too large, the code error characteristic of the main signal is deteriorated due to the error ripple effect of the discrimination signal H, so it is necessary to set it to an appropriate value. Can be expected. Further, in the embodiment, when the amplitude value of the main signal is maximum and intermediate, the modulation phase amount of the sub data signal is the same as 2α radian, but it is also possible to optimize the two separately.

Although the embodiment of the present invention has been described above in the case where the modulation method of the main data signal is 16-value quadrature amplitude modulation, the present invention is also applicable to the case of 16 values or more, that is, 32 values, 64 values, 256 values, etc. The same applies. In that case, the number of bits of the AD converters 6 and 7 is increased, the type of coefficient data of the logic circuit 91 is increased, and the phase modulation amount (α, β, etc.) of the sub data signal and the value of m are changed. do it. The sub data signal and the main data signal do not need to be synchronized in timing, and can operate even in an asynchronous state.

[Effects of the Invention] As described above, in the digital modulation / demodulation system according to the present invention, the C / N value of the sub-data signal is about 20 logs as compared with the conventional one.
(Sin β / sin α) can be improved, and the information amount of the sub data signal can be increased.

[Brief description of drawings]

FIG. 1 (a) is a block diagram showing an embodiment of a demodulating device of the present invention, FIG. 1 (b) is a block diagram showing an embodiment of a modulating device of the present invention, FIG. 2 (a) and FIG. 3B is a block diagram showing a configuration example of the sub data signal reproducing circuit in the embodiment shown in FIG. 1, and FIGS. 3A and 3B are
2 (a) or 2 (b) is an explanatory view showing the input / output relation of the logic circuit in the sub data signal reproducing circuit, and FIG. 4 is a block showing the main data signal reproducing circuit in the embodiment shown in FIG. 5 and 5 are explanatory diagrams showing the input / output relationship of the logic circuit in the main data signal reproducing circuit shown in FIG. 4, and FIG. 6 (a) is a signal arrangement diagram of a composite modulated wave of the conventional system, FIG. FIG. 1B is a signal arrangement diagram of the composite modulated wave according to the present invention. 1 ... Intermediate frequency amplifier, 2 ... VCO, 3 ... Quadrature position detector,
4, 5 ... Baseband amplifier, 6, 7 ... AD converter, 8 ...
… Sub data signal regeneration circuit, 9 …… Raw data signal regeneration circuit, 1
0 …… LPF, 11,12 …… Logic circuit, 13 …… Delay circuit, 14 …… Level discrimination circuit, 15,16 …… ROM, 17,18 …… D / A converter, 19,20
...... LPF, 21,22 …… Multiplier, 23 …… π / 2 phase shifter, 24 …… Local oscillator, 81 …… Logic circuit, 82,83 …… Multiplier, 84 …… Subtractor, 92… … Logic circuit, 93,94 …… Multiplier, 95,96 …… Adder.

Claims (3)

(57) [Claims] 1. A digital-analog output which is obtained as a result of logical operation by receiving a main data signal of a first code transmission rate and a sub-data signal of a second code transmission rate slower than the first code transmission rate. The converted signal output is given to a quadrature amplitude modulator, and the multi-valued quadrature amplitude modulation wave (the number of multi-values is more than 4) by the main data signal is subjected to phase modulation by the sub data signal. A modulator for obtaining a signal, wherein when the amplitude level becomes relatively small by changing the modulation phase amount by the sub data signal to a predetermined value according to the amplitude level of the multilevel quadrature amplitude modulation wave, A modulation device comprising means for controlling the modulation phase amount so as to be relatively large. 2. A first demodulation means which is used with the modulator according to claim 1 to obtain a first demodulation signal and a second demodulation signal by quadrature phase detection of the composite modulation signal, and the demodulation means. Second demodulation means for multi-value identifying a signal to obtain a data signal, and first demodulation means for reproducing the sub-data signal from the data signal
Reproducing means, level discrimination means for receiving the data signal and discriminating the amplitude level of the multi-valued quadrature amplitude modulated wave and outputting a discrimination signal, and corresponding to the amplitude level from the data signal in response to the discrimination signal. And a second reproducing means for reproducing the main data signal by removing the modulation phase amount. 3. An output obtained as a result of the logical operation is received as a digital analog signal by receiving a main data signal having a first code transmission rate and a sub data signal having a second code transmission rate which is slower than the first code transmission rate. The converted signal output is given to a quadrature amplitude modulator, and the multi-valued quadrature amplitude modulation wave (the number of multi-values is more than 4) by the main data signal is subjected to phase modulation by the sub data signal. When obtaining a signal, the modulation phase amount by the sub data signal is changed to a predetermined value according to the amplitude level of the multilevel quadrature amplitude modulation wave, and the modulation phase amount is changed when the amplitude level becomes relatively small. With a modulator that controls it to be relatively large,
First demodulation means for quadrature phase detection of the composite modulated signal to obtain first and second demodulation signals, second demodulation means for multivalued discrimination of the demodulation signals to obtain a data signal, and the data signal A first reproducing means for reproducing the sub-data signal from the above, a level discriminating means for receiving the data signal, discriminating the amplitude level of the multi-valued quadrature amplitude modulated wave, and outputting a discriminating signal; A digital modulation / demodulation system comprising: a demodulating device having a second reproducing means for reproducing the main data signal by removing the modulation phase amount corresponding to the amplitude level from the data signal.