JP2526540B2 - Carrier wave synchronization circuit - Google Patents
Carrier wave synchronization circuitInfo
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- JP2526540B2 JP2526540B2 JP60178501A JP17850185A JP2526540B2 JP 2526540 B2 JP2526540 B2 JP 2526540B2 JP 60178501 A JP60178501 A JP 60178501A JP 17850185 A JP17850185 A JP 17850185A JP 2526540 B2 JP2526540 B2 JP 2526540B2
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- carrier
- phase
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多値直交振幅変調波より基準搬送波を再生す
る搬送波同期回路に関する。The present invention relates to a carrier synchronizing circuit for reproducing a reference carrier from a multilevel quadrature amplitude modulation wave.
従来,種々のマイクロ波ディジタル伝送方式が実用化
の段階に入っており,最近では16QAM方式にはじまる多
値直交振幅変調方式の開発実用化が進められている。こ
のような変調方式は高能率な情報伝送が可能であるが,
外部より受ける各種の雑音に対して,その影響をこうむ
らないための余裕がますます少なくなってきている。よ
って,復調装置においては,雑音相加の少ない再生基準
搬送波を用いた同期検波方式が不可欠であり,更にその
基準搬送波を再生する際には,それに含まれるジッタ成
分が極力少なくなるような回路構成を選択する必要があ
る。Conventionally, various microwave digital transmission systems have entered the stage of practical application, and recently, the development and practical application of a multi-valued quadrature amplitude modulation system beginning with the 16QAM system has been advanced. Although such a modulation method enables highly efficient information transmission,
There is an ever-decreasing margin to prevent the effects of various types of noise from the outside. Therefore, in the demodulator, a synchronous detection method using a reproduction reference carrier with little noise addition is indispensable, and when reproducing the reference carrier, the circuit configuration is such that the jitter component contained therein is minimized. Must be selected.
その1つに,本願の発明者のうちの一人が提案した特
願昭56−15775号の“搬送波再生回路”がある。この回
路は,多値識別器の出力データを論理演算することによ
って位相誤差信号を得るように構成されており,これに
よってジッタ成分の少ない再生基準搬送波を得ることが
できる。One of them is the "carrier recovery circuit" of Japanese Patent Application No. 56-15775 proposed by one of the inventors of the present application. This circuit is configured to obtain a phase error signal by logically operating the output data of the multi-level discriminator, and thereby a reproduced reference carrier wave with less jitter component can be obtained.
しかしながら,高品質な再生基準搬送波を維持するた
めには,入力レベルは常に最適値に保つ必要があるにも
かかわらず,入力レベルの変化はその最適値を超え,前
述したC/N特性はさらに大きく劣化する。それは,変調
波の多値数が増す程に大きくなる。通常,この欠点に対
しては厳密なAGC機能を付加することで解決されるが,
特殊条件下においてはこの欠点は解決されない。即ち,
この種の搬送波再生回路は,その同期確立過程において
AGC機能が十分に動作しない時,あるいは伝送路に同相
干渉歪がある場合には,同期確立過程に長い時間を要し
たり,最悪の場合には同期確立が不能となる。本発明の
目的は,このような従来技術の問題点を解決することの
できる搬送波同期回路を提供することにある。However, in order to maintain a high quality reproduction reference carrier, the input level must always be kept at the optimum value, but the change in the input level exceeds the optimum value, and the C / N characteristics described above are further It deteriorates significantly. It increases as the multi-valued number of modulated waves increases. Usually, this problem is solved by adding a strict AGC function,
Under special conditions this drawback is not solved. That is,
This kind of carrier recovery circuit is used in the process of establishing synchronization.
If the AGC function does not operate sufficiently, or if there is common-mode interference distortion in the transmission path, it takes a long time to establish synchronization, or in the worst case, synchronization cannot be established. It is an object of the present invention to provide a carrier synchronization circuit that can solve the problems of the prior art.
本発明による搬送波同期回路は、多値直交振幅変調波
を基準搬送波で直交位相検波し、第1および第2の復調
信号を得る直交位相検出手段と、前記第1および第2の
復調信号を多値識別し、それぞれ複数列の2値データ信
号を得る多値識別手段と、該多値識別手段からそれぞれ
複数列の2値データ信号をうけて論理演算し、前記多値
直交振幅変調波が、象限判定軸と該象限判定軸にπ/4ラ
ジアンの位相関係を有する2つの位相判定軸との間に囲
まれる2つの領域を領域1(a1)および領域2(a2)と
して、該領域1および領域2の範囲内に含まれるか否か
を判別する第1の出力と、前記領域1および領域2のい
ずれに位置するかを判別する第2の出力とを得る論理演
算手段と、該論理演算手段の前記第1の出力により前記
第2の出力から位相誤差信号を抽出する誤差信号抽出手
段とを備え、前記多値識別手段の出力信号が異常同期状
態にあるときは前記誤差信号抽出手段の出力を選択して
電圧制御発振器を制御し、安定同期状態に入ったのちは
前記多値識別手段から特定の信号出力を受けて第2の位
相誤差信号を発生する搬送波再生用論理手段の出力を選
択して前記電圧制御発振器を制御するようにしたことを
特徴とする。A carrier synchronization circuit according to the present invention includes a quadrature-phase detecting means for quadrature-phase detecting a multi-valued quadrature amplitude-modulated wave with a reference carrier and obtaining first and second demodulated signals, and the first and second demodulated signals. A multivalued discriminating means for discriminating values and obtaining a binary data signal of a plurality of columns respectively, and a logical operation by receiving the binary data signals of a plurality of columns from the multivalued discriminating means, respectively, the multilevel quadrature amplitude modulated wave, The two regions surrounded by the quadrant determination axis and the two phase determination axes having a phase relationship of π / 4 radians on the quadrant determination axis are defined as area 1 (a 1 ) and area 2 (a 2 ) 1 and a logical output means for obtaining a first output for determining whether or not it is included in the range of the area 2 and a second output for determining which of the area 1 and the area 2 it is located, The phase of the first output of the logical operation means from the second output An error signal extracting means for extracting a difference signal, and when the output signal of the multi-level discriminating means is in an abnormal synchronization state, the output of the error signal extracting means is selected to control the voltage controlled oscillator to obtain a stable synchronization state. After entering, the output of the carrier recovery logic means for receiving the specific signal output from the multi-level identification means and generating the second phase error signal is selected to control the voltage controlled oscillator. Characterize.
次に,本発明による搬送波同期回路について実施例を
挙げ,図面を参照して説明する。Next, a carrier synchronization circuit according to the present invention will be described with reference to the drawings with reference to embodiments.
第1図は本発明を64QAM変調波に適用した場合の実施
例の構成をブロック図により示したものである。図にお
いて,1は直交位相検波器(QAMDET),2,3は可変減衰器
(ATT),4,5は5ビットA/D変換器,6,7はAGC回路,8はRO
M,9は搬送波再生用論理回路,10はD型フリップフロッ
プ,11はOR回路,12はAND回路,13は選択回路(SW),14は
低域ろ波器(LPF),15は電圧制御発振器(VCO)であ
る。以下,この回路の動作について説明すると,64QAM変
調波は直交位相検波器1に入り,VCO15の出力である基準
搬送波で同期検波され,復調信号PおよびQに変換され
る。復調された信号PおよびQはそれぞれATT2及び3に
加えられ,ここでAGC6および7から供給される制御信号
によりそれぞれA/D変換器4および5の入力レベルを最
適レベルに保つように制御される。A/D変換器4,5は,こ
の例においては5ビットが適用されており,MSB(最上位
桁)のD1からD3まで主データ信号として外部に送出され
る。FIG. 1 is a block diagram showing the configuration of an embodiment when the present invention is applied to a 64QAM modulated wave. In the figure, 1 is a quadrature detector (QAMDET), 2 and 3 are variable attenuators (ATT), 4 and 5 are 5-bit A / D converters, 6 and 7 are AGC circuits, and 8 is RO.
M, 9 is a carrier recovery logic circuit, 10 is a D-type flip-flop, 11 is an OR circuit, 12 is an AND circuit, 13 is a selection circuit (SW), 14 is a low-pass filter (LPF), and 15 is voltage control. It is an oscillator (VCO). The operation of this circuit will be described below. The 64QAM modulated wave enters the quadrature phase detector 1, is synchronously detected by the reference carrier which is the output of the VCO 15, and is converted into demodulated signals P and Q. The demodulated signals P and Q are added to ATT2 and 3, respectively, and are controlled by the control signals supplied from AGC6 and 7 so as to keep the input levels of the A / D converters 4 and 5 at optimum levels. . In this example, 5 bits are applied to the A / D converters 4 and 5, and MSB (most significant digit) D 1 to D 3 are transmitted to the outside as main data signals.
ROM8は本発明の特徴となる搬送波同期用の制御信号を
作成する論理演算手段として設けられている。この回路
の動作について第2図(a)および(b)を参照して説
明する。図(a)は64QAM変調波の信号配置図を示して
おり,図中P0軸およびQ0軸は,各信号点が属する象限を
判別する象限判定軸であり,A0軸およびB0軸は象限判定
軸とπ/4ラジアンの位相関係を有する軸を示し,ここで
は位置判別軸と定義する。ROM8の出力S2はA1軸とA2軸,
B1軸とB2軸とにそれぞれ囲まれた領域,即ち領域a1に領
域a2をプラスした領域に信号点が入った場合,“1"の信
号を出力する。又,出力S1は先の領域をP0軸及びQ0軸を
境界として領域a1と領域a2に分け,信号点が領域a1に入
ったとき“1"の信号,領域a2に入った時“0"の信号を出
力する。図(b)は,図(a)の第1象限を拡大したも
のであり,軸A0〜A1を5ビットで近似した場合を示して
いる。このなかで,領域a3は5ビットで近似した場合の
不感点を表わしている。よって,A/D変換器4,5のビット
数を増せば領域a3を小さくすることができる。The ROM 8 is provided as a logical operation means for creating a control signal for carrier wave synchronization, which is a feature of the present invention. The operation of this circuit will be described with reference to FIGS. 2 (a) and 2 (b). Figure (a) shows the signal arrangement of the 64QAM modulated wave. In the figure, the P 0 axis and the Q 0 axis are the quadrant determination axes that determine the quadrant to which each signal point belongs, the A 0 axis and the B 0 axis. Indicates an axis that has a phase relationship of π / 4 radians with the quadrant determination axis, and is defined as the position determination axis here. Output S 2 of ROM8 is A 1 axis and A 2 axis,
When a signal point enters the area surrounded by the B 1 axis and the B 2 axis, that is, the area obtained by adding the area a 2 to the area a 1 , the signal of “1” is output. In addition, the output S 1 is divided into an area a 1 and an area a 2 with the previous area as the boundaries of the P 0 axis and the Q 0 axis, and when the signal point enters the area a 1 , it becomes a “1” signal, area a 2 . When it enters, it outputs a "0" signal. FIG. 2B is an enlarged view of the first quadrant of FIG. 1A and shows a case where the axes A 0 to A 1 are approximated by 5 bits. Of these, the area a 3 represents a dead point in the case of approximation with 5 bits. Therefore, the area a 3 can be reduced by increasing the number of bits of the A / D converters 4 and 5.
ROM8の出力S1は信号点の位相回転に対して一方向の出
力を出すため,位相誤差信号として役立てられる。しか
し,この位相誤差信号はA0,B0軸上(又はその付近)に
位置する信号点からしか検出できず,A0,B0軸から離れ
ている信号点からは雑音を受けるのみ誤差信号としての
寄与は受けない。よって,A0,B0軸から離れている信号
点から情報を受けないように構成することが望ましく,
そのために,D型フリップフロップ10によりS1の信号から
領域a1及び領域a2以外の信号点の情報をとり除いてい
る。以上の操作によって,フリップフロップ10の出力を
LPF14を介してVCO15に供給すれば,第2図(a)の状態
で搬送波同期が確立する。ここで,入力レベルが変化し
たとしても,A0,B0軸上の信号点は軸上を動くのみで、
軸から離れることはない。したがって,第1図による搬
送波同期回路は入力レベルに依存せずに良好な動作をす
る。領域a1及びa2をA0,B0軸上以外の信号点を含まない
ように設定すれば,ジッタ成分の少ない基準搬送波を再
生することができるが,あまり狭くすると第2図(a)
に示された状態からある伝相回転をもったところで安定
するところの,いわゆる擬似引込現象を生ずるので,第
2図(a)の状態でA0,B0軸上の信号点を含まない程度
に広げた領域に設定するのが望ましい。但し,多値数と
か,伝送路状態に依存するために一義的には決められな
い。The output S 1 of the ROM 8 is useful as a phase error signal because it outputs in one direction with respect to the phase rotation of the signal point. However, the phase error signal A 0, B 0 can not be detected only from a signal point located on the axis (or near), A 0, B 0 error signal only subjected to noise from the signal point that is remote from the axis Will not be contributed. Therefore, it is desirable to configure so that information is not received from the signal points that are far from the A 0 and B 0 axes.
Therefore, the D-type flip-flop 10 removes the information of the signal points other than the areas a 1 and a 2 from the signal of S 1 . By the above operation, the output of the flip-flop 10
If it is supplied to the VCO 15 via the LPF 14, carrier synchronization is established in the state shown in FIG. Here, even if the input level changes, the signal points on the A 0 and B 0 axes only move on the axis,
It never leaves the axis. Therefore, the carrier synchronization circuit according to FIG. 1 operates well regardless of the input level. If the regions a 1 and a 2 are set so as not to include signal points other than those on the A 0 and B 0 axes, the reference carrier with a small jitter component can be reproduced, but if it is too narrow, it will be shown in FIG. 2 (a).
Since a so-called pseudo-pull-in phenomenon occurs, which is stable when there is a certain phase rotation from the state shown in Fig. 2, the signal points on the A 0 and B 0 axes are not included in the state of Fig. 2 (a). It is desirable to set it in the area widened to. However, it cannot be uniquely determined because it depends on the multi-valued number or the state of the transmission path.
A0,B0軸を近似するために必要なビット数は,主信号
を再生するに必要なビット数から2〜3ビット増せば十
分と思われる。本発明による搬送波同期回路は入力レベ
ルに依存しない利点を有しているが,入力変調波の信号
点のうちの1部から誤差信号を検出しているため,再生
搬送波に含まれるジッタ成分は従来の搬送波同期回路に
よるそれと比較すると若干多くなる。したがって,搬送
波同期回路の同期が確立した安定状態では,従来の搬送
波同期回路を用いた方が得策であり,これは多値数が増
す程に効果を発揮する。第1図における選択回路13は両
者を切替えるもので,AGC回路6,7からALM信号が消失した
時,即ち,この搬送波同期回路自身が安定動作に入った
時,搬送再生用論理回路9の出力がLPF14を介してVCO15
に制御信号として与えられる。なお,搬送波再生用論理
回路9の具体的な構成および動作は,前述した特願昭56
−15775号の明細書に詳述されているので,ここでは省
略する。It seems sufficient to increase the number of bits required to approximate the A 0 and B 0 axes by 2 to 3 bits from the number of bits required to reproduce the main signal. The carrier synchronization circuit according to the present invention has an advantage that it does not depend on the input level, but since the error signal is detected from a part of the signal points of the input modulated wave, the jitter component included in the reproduced carrier is conventionally. It is slightly larger than that of the carrier synchronization circuit. Therefore, in the stable state where the synchronization of the carrier synchronization circuit is established, it is better to use the conventional carrier synchronization circuit, and this becomes more effective as the number of multivalues increases. The selection circuit 13 in FIG. 1 switches between the two, and when the ALM signal disappears from the AGC circuits 6 and 7, that is, when the carrier synchronization circuit itself enters stable operation, the output of the carrier reproduction logic circuit 9 is output. VCO15 through LPF14
Given as a control signal. The specific configuration and operation of the carrier wave reproducing logic circuit 9 are described in Japanese Patent Application No.
Since it is described in detail in the specification of -15775, it is omitted here.
第3図(a)はAGC6,7の具体的な構成をAGC6の場合を
例に挙げてブロック図により示したものであり,第3図
(b)はその動作を説明するための図である。この図に
おいて,6−1は論理回路,6−2はフリップフロップ,6−
3は検出回路である。論理回路6−1の出力Sは,図
(b)における領域C0に信号点が入ったとき“1"の出力
を出し,出力Rは領域C1に信号点が入った時“1"の出力
を出す。これらの出力はフリップフロップ6−2を介し
て可変減衰器2,3の制御信号AGC CONTとなる。ここで,AG
C機能が正常に動作していない時,即ち信号点が領域
C0,あるいはC1のどちらか一方のみ入り込んでいる時に
は,フリップフロップ6−2の出力はDCレベルとなる。
又,正常時にはマーク率1/2のデータ信号となる。よっ
て,この両者の差を検出回路6−3により検出し,異常
時にALM信号を送出するようになっている。FIG. 3 (a) is a block diagram showing a specific configuration of the AGC 6, 7 by taking the case of the AGC 6 as an example, and FIG. 3 (b) is a diagram for explaining its operation. . In this figure, 6-1 is a logic circuit, 6-2 is a flip-flop, 6-
3 is a detection circuit. The output S of the logic circuit 6-1 outputs "1" when the signal point enters the area C 0 in FIG. (B), and the output R of "1" when the signal point enters the area C 1 . Print the output. These outputs become the control signal AGC CONT of the variable attenuators 2 and 3 via the flip-flop 6-2. Where AG
When the C function is not operating normally, that is, the signal point is in the area
When only one of C 0 and C 1 enters, the output of the flip-flop 6-2 becomes DC level.
Also, when the signal is normal, the data signal has a mark rate of 1/2. Therefore, the difference between the two is detected by the detection circuit 6-3, and the ALM signal is transmitted when an abnormality occurs.
再び第1図を参照し,フリップフロップ10の出力によ
って制御される搬送波の同期状態は入力レベルに依存せ
ずに成立するが,搬送波再生用論理回路9の出力による
搬送波同期状態は入力レベルに依存するため,フリップ
フロップ10の出力から論理回路9の出力に切替える際に
は,AGC回路6,7が正常に動作しているか否かを確認する
ことが不可欠である。そのため,選択回路13を制御する
信号にAGC6,7のALM信号を用いている。なお,選択回路1
3の制御信号として,この他に符号誤り率特性検出回路1
6からの情報を用いることもできる。Referring again to FIG. 1, the carrier synchronization state controlled by the output of the flip-flop 10 is established independently of the input level, but the carrier synchronization state produced by the output of the carrier recovery logic circuit 9 depends on the input level. Therefore, when switching from the output of the flip-flop 10 to the output of the logic circuit 9, it is essential to check whether the AGC circuits 6 and 7 are operating normally. Therefore, the ALM signals of AGC6 and 7 are used as signals for controlling the selection circuit 13. The selection circuit 1
In addition to this, as the control signal of 3, the code error rate characteristic detection circuit 1
Information from 6 can also be used.
なお,上記の実施例は,64QAMシステムに適用した場合
について説明したが,本発明はこれに限定されるもので
はなく,4QAM(4PSK)以上の多値直交振幅変調システム
に適用可能であることは言うまでもない。勿論,64QAMシ
ステム以外のシステムに変更する場合には,A/D変換器4,
5のビット数,ROM8の記憶容量の変更のみで良い。Although the above embodiment has been described with respect to the case where it is applied to a 64QAM system, the present invention is not limited to this, and is applicable to a multilevel quadrature amplitude modulation system of 4QAM (4PSK) or more. Needless to say. Of course, when changing to a system other than 64QAM system, A / D converter 4,
Only the number of bits of 5 and the storage capacity of ROM8 need be changed.
以上の説明により明らかなように,本発明によれば,
入力直交振幅変調波の多値数が大きい場合にも,その入
力レベルに依存しないで同期をとることができ,これに
よって,伝送系に同相の干渉歪が存在したり,AGC機能が
十分に動作しないときにも,短時間で同期を確立するこ
とが可能となり,システムの信頼性を向上すべくその得
られる効果は大きい。As apparent from the above description, according to the present invention,
Even if the input quadrature amplitude modulated wave has a large number of levels, synchronization can be achieved without depending on the input level. This allows in-phase interference distortion to exist in the transmission system and the AGC function to operate sufficiently. Even when not doing so, it is possible to establish synchronization in a short time, and the resulting effect is great in order to improve system reliability.
第1図は本発明による実施例の構成を示すブロック図,
第2図(a)および(b)は,第1図の実施例に適用さ
れるそれぞれQAM変調波の信号配置図およびその第1象
限の拡大図,第3図(a)および(b)は,第1図にお
けるAGC回路のそれぞれ具体的な構成例を示すブロック
図およびその動作を説明するための図である。 図において,1は直交位相検出器,2,3は可変減衰器,4,5は
A/D変換器,6,7はAGC回路,8はROM,9は搬送波再生用論理
回路,10はD型フリップフロップ,11はOR回路,12はAND回
路,13は選択回路,14は低減ろ波器,15は電圧制御発振器
である。FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention,
2 (a) and 2 (b) are respectively a signal arrangement diagram of the QAM modulated wave applied to the embodiment of FIG. 1 and an enlarged view of its first quadrant, and FIGS. 3 (a) and 3 (b) are 2 is a block diagram showing a specific configuration example of the AGC circuit in FIG. 1 and a diagram for explaining the operation thereof. In the figure, 1 is a quadrature detector, 2 and 3 are variable attenuators, and 4 and 5 are
A / D converter, 6 and 7 are AGC circuits, 8 is ROM, 9 is carrier reproduction logic circuit, 10 is D type flip-flop, 11 is OR circuit, 12 is AND circuit, 13 is selection circuit, 14 is reduction Filter 15 is a voltage controlled oscillator.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松浦 徹 東京都港区芝5丁目33番1号 日本電気 株式会社内 (56)参考文献 特開 昭59−148459(JP,A) 特開 昭57−131151(JP,A) 昭和50年度電子通信学会総合全国大会 講演論文集,〔分冊8〕,p.1822 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Matsuura 5-33-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (56) References JP-A-59-148459 (JP, A) JP-A-57 -131151 (JP, A) Proceedings of the 50th National Conference of the Institute of Electronics, Information and Communication Engineers, [Volume 8], p. 1822
Claims (1)
相検波し、第1および第2の復調信号を得る直交位相検
波手段と、前記第1および第2の復調信号を多値識別
し、それぞれ少なくとも主信号ビットプラス2ビットか
らなる複数列の2値データ信号を得る多値識別手段と、
該多値識別手段からそれぞれ複数列の2値データ信号を
うけて論理演算し、前記多値直交振幅変調波が、象限判
定軸と該象限判定軸にπ/4ラジアンの位相関係を有する
2つの位相判定軸との間に囲まれる2つの領域を領域1
(a1)および領域2(a2)として、該領域1および領域
2の範囲に含まれるか否かを判別する第1の出力と、前
記領域1および領域2のいずれに位置するかを判別する
第2の出力とを得る論理演算手段と、該論理演算手段の
前記第1の出力により前記第2の出力から位相誤差信号
を抽出する誤差信号抽出手段とを備え、前記多値識別手
段の出力信号が異常同期状態にあるときは前記誤差信号
抽出手段の出力を選択して電圧制御発振器を制御し、安
定同期状態に入ったのちは前記多値識別手段殻の特定の
信号出力を受けて第2の位相誤差信号を発生する搬送波
再生用論理手段の出力を選択して前記電圧制御発振器を
制御するようにしたことを特徴とする搬送波同期回路。1. A quadrature phase detecting means for quadrature phase detecting a multi-valued quadrature amplitude modulated wave with a reference carrier to obtain first and second demodulated signals, and multi-valued discrimination of the first and second demodulated signals. Multi-value identifying means for obtaining a plurality of columns of binary data signals each consisting of at least a main signal bit plus 2 bits,
A logical operation is performed by receiving a plurality of columns of binary data signals from the multi-level discriminating means, and the multi-level quadrature amplitude modulation wave has two quadrant discriminating axes and a phase relationship of π / 4 radians on the quadrant discriminating axes. Area 1 is defined as the two areas surrounded by the phase determination axis.
As (a 1 ) and area 2 (a 2 ), a first output for determining whether or not the area is included in the range of the area 1 and the area 2 and determining which of the area 1 and the area 2 is located Of the multi-level discriminating means, and a logic operation means for obtaining a second output that outputs a phase error signal from the second output by the first output of the logic operation means. When the output signal is in the abnormal synchronization state, the output of the error signal extraction means is selected to control the voltage controlled oscillator, and after entering the stable synchronization state, the specific signal output of the multi-level discrimination means shell is received. A carrier synchronizing circuit characterized in that the voltage controlled oscillator is controlled by selecting an output of a carrier reproducing logic means for generating a second phase error signal.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60178501A JP2526540B2 (en) | 1985-08-15 | 1985-08-15 | Carrier wave synchronization circuit |
EP86111275A EP0212582B1 (en) | 1985-08-15 | 1986-08-14 | Demodulation system capable of establishing synchronization in a transient state |
DE8686111275T DE3687249T2 (en) | 1985-08-15 | 1986-08-14 | DEMODULATION SYSTEM SUITABLE FOR SYNCHRONIZATION PRODUCTION IN A TRANSITIONAL STATE. |
CA000516027A CA1262266A (en) | 1985-08-15 | 1986-08-15 | Demodulation system capable of establishing synchronization in a transient state |
AU61198/86A AU584555B2 (en) | 1985-08-15 | 1986-08-15 | Demodulation system capable of establishing synchronization in a transient state |
US06/896,985 US4757266A (en) | 1985-08-15 | 1986-08-15 | Demodulation system capable of establishing synchronization in a transient state |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60178501A JP2526540B2 (en) | 1985-08-15 | 1985-08-15 | Carrier wave synchronization circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6239943A JPS6239943A (en) | 1987-02-20 |
JP2526540B2 true JP2526540B2 (en) | 1996-08-21 |
Family
ID=16049564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60178501A Expired - Lifetime JP2526540B2 (en) | 1985-08-15 | 1985-08-15 | Carrier wave synchronization circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2526540B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2927929B2 (en) * | 1990-10-29 | 1999-07-28 | 日本電気株式会社 | Carrier synchronization circuit |
JP2727926B2 (en) * | 1993-08-13 | 1998-03-18 | 日本電気株式会社 | Demodulator |
JP2669322B2 (en) * | 1993-12-01 | 1997-10-27 | 日本電気株式会社 | Demodulator |
-
1985
- 1985-08-15 JP JP60178501A patent/JP2526540B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
昭和50年度電子通信学会総合全国大会講演論文集,〔分冊8〕,p.1822 |
Also Published As
Publication number | Publication date |
---|---|
JPS6239943A (en) | 1987-02-20 |
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