JP2526540B2 - Carrier wave synchronization circuit - Google Patents

Description

The present invention relates to a carrier synchronizing circuit for reproducing a reference carrier from a multilevel quadrature amplitude modulation wave.

[Conventional technology]

Conventionally, various microwave digital transmission systems have entered the stage of practical application, and recently, the development and practical application of a multi-valued quadrature amplitude modulation system beginning with the 16QAM system has been advanced. Although such a modulation method enables highly efficient information transmission,
There is an ever-decreasing margin to prevent the effects of various types of noise from the outside. Therefore, in the demodulator, a synchronous detection method using a reproduction reference carrier with little noise addition is indispensable, and when reproducing the reference carrier, the circuit configuration is such that the jitter component contained therein is minimized. Must be selected.

One of them is the "carrier recovery circuit" of Japanese Patent Application No. 56-15775 proposed by one of the inventors of the present application. This circuit is configured to obtain a phase error signal by logically operating the output data of the multi-level discriminator, and thereby a reproduced reference carrier wave with less jitter component can be obtained.

[Problems to be solved by the invention]

However, in order to maintain a high quality reproduction reference carrier, the input level must always be kept at the optimum value, but the change in the input level exceeds the optimum value, and the C / N characteristics described above are further It deteriorates significantly. It increases as the multi-valued number of modulated waves increases. Usually, this problem is solved by adding a strict AGC function,
Under special conditions this drawback is not solved. That is,
This kind of carrier recovery circuit is used in the process of establishing synchronization.
If the AGC function does not operate sufficiently, or if there is common-mode interference distortion in the transmission path, it takes a long time to establish synchronization, or in the worst case, synchronization cannot be established. It is an object of the present invention to provide a carrier synchronization circuit that can solve the problems of the prior art.

[Means for solving problems]

A carrier synchronization circuit according to the present invention includes a quadrature-phase detecting means for quadrature-phase detecting a multi-valued quadrature amplitude-modulated wave with a reference carrier and obtaining first and second demodulated signals, and the first and second demodulated signals. A multivalued discriminating means for discriminating values and obtaining a binary data signal of a plurality of columns respectively, and a logical operation by receiving the binary data signals of a plurality of columns from the multivalued discriminating means, respectively, the multilevel quadrature amplitude modulated wave, The two regions surrounded by the quadrant determination axis and the two phase determination axes having a phase relationship of π / 4 radians on the quadrant determination axis are defined as area 1 (a ₁ ) and area 2 (a ₂ ) 1 and a logical output means for obtaining a first output for determining whether or not it is included in the range of the area 2 and a second output for determining which of the area 1 and the area 2 it is located, The phase of the first output of the logical operation means from the second output An error signal extracting means for extracting a difference signal, and when the output signal of the multi-level discriminating means is in an abnormal synchronization state, the output of the error signal extracting means is selected to control the voltage controlled oscillator to obtain a stable synchronization state. After entering, the output of the carrier recovery logic means for receiving the specific signal output from the multi-level identification means and generating the second phase error signal is selected to control the voltage controlled oscillator. Characterize.

Example of Invention

Next, a carrier synchronization circuit according to the present invention will be described with reference to the drawings with reference to embodiments.

FIG. 1 is a block diagram showing the configuration of an embodiment when the present invention is applied to a 64QAM modulated wave. In the figure, 1 is a quadrature detector (QAMDET), 2 and 3 are variable attenuators (ATT), 4 and 5 are 5-bit A / D converters, 6 and 7 are AGC circuits, and 8 is RO.
M, 9 is a carrier recovery logic circuit, 10 is a D-type flip-flop, 11 is an OR circuit, 12 is an AND circuit, 13 is a selection circuit (SW), 14 is a low-pass filter (LPF), and 15 is voltage control. It is an oscillator (VCO). The operation of this circuit will be described below. The 64QAM modulated wave enters the quadrature phase detector 1, is synchronously detected by the reference carrier which is the output of the VCO 15, and is converted into demodulated signals P and Q. The demodulated signals P and Q are added to ATT2 and 3, respectively, and are controlled by the control signals supplied from AGC6 and 7 so as to keep the input levels of the A / D converters 4 and 5 at optimum levels. . In this example, 5 bits are applied to the A / D converters 4 and 5, and MSB (most significant digit) D ₁ to D ₃ are transmitted to the outside as main data signals.

The ROM 8 is provided as a logical operation means for creating a control signal for carrier wave synchronization, which is a feature of the present invention. The operation of this circuit will be described with reference to FIGS. 2 (a) and 2 (b). Figure (a) shows the signal arrangement of the 64QAM modulated wave. In the figure, the P ₀ axis and the Q ₀ axis are the quadrant determination axes that determine the quadrant to which each signal point belongs, the A ₀ axis and the B ₀ axis. Indicates an axis that has a phase relationship of π / 4 radians with the quadrant determination axis, and is defined as the position determination axis here. Output S ₂ of ROM8 is A ₁ axis and A ₂ axis,
When a signal point enters the area surrounded by the B ₁ axis and the B ₂ axis, that is, the area obtained by adding the area a ₂ to the area a ₁ , the signal of “1” is output. In addition, the output S ₁ is divided into an area a ₁ and an area a ₂ with the previous area as the boundaries of the P ₀ axis and the Q ₀ axis, and when the signal point enters the area a ₁ , it becomes a “1” signal, area a ₂ . When it enters, it outputs a "0" signal. FIG. 2B is an enlarged view of the first quadrant of FIG. 1A and shows a case where the axes A _{0 to} A ₁ are approximated by 5 bits. Of these, the area a ₃ represents a dead point in the case of approximation with 5 bits. Therefore, the area a ₃ can be reduced by increasing the number of bits of the A / D converters 4 and 5.

The output S ₁ of the ROM 8 is useful as a phase error signal because it outputs in one direction with respect to the phase rotation of the signal point. However, the phase error signal A _0, B ₀ can not be detected only from a signal point located on the axis (or near), A _0, B ₀ error signal only subjected to noise from the signal point that is remote from the axis Will not be contributed. Therefore, it is desirable to configure so that information is not received from the signal points that are far from the A ₀ and B ₀ axes.
Therefore, the D-type flip-flop 10 removes the information of the signal points other than the areas a ₁ and a ₂ from the signal of S ₁ . By the above operation, the output of the flip-flop 10
If it is supplied to the VCO 15 via the LPF 14, carrier synchronization is established in the state shown in FIG. Here, even if the input level changes, the signal points on the A ₀ and B ₀ axes only move on the axis,
It never leaves the axis. Therefore, the carrier synchronization circuit according to FIG. 1 operates well regardless of the input level. If the regions a ₁ and a ₂ are set so as not to include signal points other than those on the A ₀ and B ₀ axes, the reference carrier with a small jitter component can be reproduced, but if it is too narrow, it will be shown in FIG. 2 (a).
Since a so-called pseudo-pull-in phenomenon occurs, which is stable when there is a certain phase rotation from the state shown in Fig. 2, the signal points on the A ₀ and B ₀ axes are not included in the state of Fig. 2 (a). It is desirable to set it in the area widened to. However, it cannot be uniquely determined because it depends on the multi-valued number or the state of the transmission path.

It seems sufficient to increase the number of bits required to approximate the A ₀ and B ₀ axes by 2 to 3 bits from the number of bits required to reproduce the main signal. The carrier synchronization circuit according to the present invention has an advantage that it does not depend on the input level, but since the error signal is detected from a part of the signal points of the input modulated wave, the jitter component included in the reproduced carrier is conventionally. It is slightly larger than that of the carrier synchronization circuit. Therefore, in the stable state where the synchronization of the carrier synchronization circuit is established, it is better to use the conventional carrier synchronization circuit, and this becomes more effective as the number of multivalues increases. The selection circuit 13 in FIG. 1 switches between the two, and when the ALM signal disappears from the AGC circuits 6 and 7, that is, when the carrier synchronization circuit itself enters stable operation, the output of the carrier reproduction logic circuit 9 is output. VCO15 through LPF14
Given as a control signal. The specific configuration and operation of the carrier wave reproducing logic circuit 9 are described in Japanese Patent Application No.
Since it is described in detail in the specification of -15775, it is omitted here.

FIG. 3 (a) is a block diagram showing a specific configuration of the AGC 6, 7 by taking the case of the AGC 6 as an example, and FIG. 3 (b) is a diagram for explaining its operation. . In this figure, 6-1 is a logic circuit, 6-2 is a flip-flop, 6-
3 is a detection circuit. The output S of the logic circuit 6-1 outputs "1" when the signal point enters the area C ₀ in FIG. (B), and the output R of "1" when the signal point enters the area C ₁ . Print the output. These outputs become the control signal AGC CONT of the variable attenuators 2 and 3 via the flip-flop 6-2. Where AG
When the C function is not operating normally, that is, the signal point is in the area
When only _one of C ₀ and C ₁ enters, the output of the flip-flop 6-2 becomes DC level.
Also, when the signal is normal, the data signal has a mark rate of 1/2. Therefore, the difference between the two is detected by the detection circuit 6-3, and the ALM signal is transmitted when an abnormality occurs.

Referring again to FIG. 1, the carrier synchronization state controlled by the output of the flip-flop 10 is established independently of the input level, but the carrier synchronization state produced by the output of the carrier recovery logic circuit 9 depends on the input level. Therefore, when switching from the output of the flip-flop 10 to the output of the logic circuit 9, it is essential to check whether the AGC circuits 6 and 7 are operating normally. Therefore, the ALM signals of AGC6 and 7 are used as signals for controlling the selection circuit 13. The selection circuit 1
In addition to this, as the control signal of 3, the code error rate characteristic detection circuit 1
Information from 6 can also be used.

Although the above embodiment has been described with respect to the case where it is applied to a 64QAM system, the present invention is not limited to this, and is applicable to a multilevel quadrature amplitude modulation system of 4QAM (4PSK) or more. Needless to say. Of course, when changing to a system other than 64QAM system, A / D converter 4,
Only the number of bits of 5 and the storage capacity of ROM8 need be changed.

〔The invention's effect〕

As apparent from the above description, according to the present invention,
Even if the input quadrature amplitude modulated wave has a large number of levels, synchronization can be achieved without depending on the input level. This allows in-phase interference distortion to exist in the transmission system and the AGC function to operate sufficiently. Even when not doing so, it is possible to establish synchronization in a short time, and the resulting effect is great in order to improve system reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention,
2 (a) and 2 (b) are respectively a signal arrangement diagram of the QAM modulated wave applied to the embodiment of FIG. 1 and an enlarged view of its first quadrant, and FIGS. 3 (a) and 3 (b) are 2 is a block diagram showing a specific configuration example of the AGC circuit in FIG. 1 and a diagram for explaining the operation thereof. In the figure, 1 is a quadrature detector, 2 and 3 are variable attenuators, and 4 and 5 are
A / D converter, 6 and 7 are AGC circuits, 8 is ROM, 9 is carrier reproduction logic circuit, 10 is D type flip-flop, 11 is OR circuit, 12 is AND circuit, 13 is selection circuit, 14 is reduction Filter 15 is a voltage controlled oscillator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toru Matsuura 5-33-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (56) References JP-A-59-148459 (JP, A) JP-A-57 -131151 (JP, A) Proceedings of the 50th National Conference of the Institute of Electronics, Information and Communication Engineers, [Volume 8], p. 1822

Claims (1)

(57) [Claims] 1. A quadrature phase detecting means for quadrature phase detecting a multi-valued quadrature amplitude modulated wave with a reference carrier to obtain first and second demodulated signals, and multi-valued discrimination of the first and second demodulated signals. Multi-value identifying means for obtaining a plurality of columns of binary data signals each consisting of at least a main signal bit plus 2 bits,
A logical operation is performed by receiving a plurality of columns of binary data signals from the multi-level discriminating means, and the multi-level quadrature amplitude modulation wave has two quadrant discriminating axes and a phase relationship of π / 4 radians on the quadrant discriminating axes. Area 1 is defined as the two areas surrounded by the phase determination axis.
As (a ₁ ) and area 2 (a ₂ ), a first output for determining whether or not the area is included in the range of the area 1 and the area 2 and determining which of the area 1 and the area 2 is located Of the multi-level discriminating means, and a logic operation means for obtaining a second output that outputs a phase error signal from the second output by the first output of the logic operation means. When the output signal is in the abnormal synchronization state, the output of the error signal extraction means is selected to control the voltage controlled oscillator, and after entering the stable synchronization state, the specific signal output of the multi-level discrimination means shell is received. A carrier synchronizing circuit characterized in that the voltage controlled oscillator is controlled by selecting an output of a carrier reproducing logic means for generating a second phase error signal.