JP2927929B2 - Carrier synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a carrier synchronization circuit, and more particularly to a carrier synchronization circuit used in a 2 ^N (N is an integer of 2 or more) value quadrature amplitude modulation system.

[Conventional technology]

FIG. 6 is a block diagram of a carrier synchronization circuit necessary for reproducing a reference carrier signal for receiving and demodulating a signal subjected to 16-level quadrature amplitude modulation (hereinafter referred to as 16QAM) using a conventional digitized carrier synchronization circuit. As shown in the figure, a signal k subjected to 16QAM is input from the input terminal of the figure. On the other hand, two carrier signals r1 and r2 having a π / 2 radian phase difference generated by a voltage controlled oscillator (hereinafter referred to as VCO) 25 and a π / 2 phase shifter 27 are input to multipliers 16 and 17, respectively. And demodulated baseband signals b1 and b2 by synchronous detection. The baseband signals b1 and b2 are input to A / D converters 18 and 19, and a clock recovery circuit 26 generates a clock as a timing signal.
A / D converter identified by clocks P1 and P2 reproduced by
From P18, P19, digital output signals c1, c2, c3 of Pch and digital output signals d1, d2, d3 of Qch are obtained.

FIG. 4 is a diagram for explaining the operation of the A / D converters 18 and 19 for converting the analog signal levels b1 and b2 into digital output signals X1 to X4 in FIG. 4, and the general 16-level quadrature amplitude modulation in FIG. A description will be given with reference to the signal arrangement explanatory diagram. As shown in FIG. 5, each of the 16-valued signal points is divided into regions of P1 to P4 on the Pch side and Q1 to Q4 on the Qch side at the identification level points, respectively.
Further, each area is divided into P1A and P1B areas and Q1A and Q1B areas vertically and horizontally around the signal point. Now, the transmitted signal point is, for example, P1 in the area of P1 and Q1.
4A, the digital output signals c1, c2, c3 are 1, 1, 1 and d1, d2, d3 are from the chart of FIG.
1,1,0 are output. Here, the digital output signal c1 is
Represents the first bit (MSB) of the in-phase component signal (Pch), and the Pc of the quaternary demodulated baseband signal b1 together with the second bit c2
It becomes the Pch output signal Wp of the identification result as h (see FIG. 6). c3 is the third bit of the Pch and represents an amplitude error signal which is a deviation from a true signal point. d1 represents the first bit (MSB) of the quadrature component (Qch), and 4 together with d2 of the second bit.
Qch output signal W as a result of discrimination of value demodulated baseband signal b2
It becomes _Q (see FIG. 6). d3 is the third bit of Qch and represents an amplitude error signal which is a deviation from a true signal point. Here, the synchronization operation of the carrier synchronization circuit is performed by digital signals c1, d3,
Control operations are performed on all 16 signal points using d1 and c3 to synchronize the carrier. The exclusive ORs 20 and 21 are the first bit c1 of Pch and the error signal d3 of Qch, and the first bit c1 of Qch and Pch
By taking an exclusive OR with the error signal d3 of, and taking the difference by the subtractor 22,
The phase control signal μ can be obtained. To further explain with reference to FIG. 4, if the transmitted signal point is in the area of P1A, Q1B, for example, the deviation from the true value is the amplitude error signal.
P1A, Q1 specified by c1 = 1, d3 = 0 and d1 = 1, c3 = 1
It can be seen that there is a shift in the area B.

The digital output × 4, (c4, d4) in FIG. 4 is added for the purpose of explaining the present invention and does not exist in the conventional example.

Returning to the above description, the phase control signal μ in FIG. 6 is input to the flip-flop 23 and the reproduction clock P3
And the phase control signal q2 from which the noise component has been removed by the loop filter 24.
Thus, the voltage control starter 25 was controlled to control the carrier synchronization signal in the phase pull-in direction.

[Problems to be solved by the invention]

The carrier synchronization circuit used in the above-described conventional quadrature amplitude modulation circuit generates a carrier phase control signal from a digital signal obtained as a result of identifying a deviation of a signal point from a true value. Therefore, the phase error becomes large, and when the carrier phase control signal is generated by the orthogonal phase detection plane, that is, the signal having the unequal distance from the signal point, the control is erroneously performed, or the carrier synchronization is lost. When the demodulated signal is not correctly identified, especially when the error of the digital signal as the identification result becomes large, there is a disadvantage that the loop gain decreases, the carrier phase control voltage decreases, and the synchronization pull-in range decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a carrier synchronization circuit that further restricts an actual area of a transmitted signal point and that forms a normal phase control loop only when the signal point is within a predetermined limited area. Is to do.

[Means for solving the problem]

A carrier synchronization circuit according to the present invention is used for a multi-level quadrature amplitude modulation system having a multi-level number of 2 ^N (N is an even number of 2 or more) and a carrier generation circuit (hereinafter referred to as VCO) and synchronization of a carrier signal of the VCO In a carrier synchronous circuit having a control loop (hereinafter referred to as APC), 2 ^{N / 2 is} added to the P channel at an identification level point of each of 2 ^N signal points.
Pieces, 2 ^N was divided into 2 ^{N / 2} pieces of region Q channel (N is the N in the same) as the number of 1s region sub region of the divided regions, the analog signal of the transmission signal point is input to the sub-region A / D for P channel and Q channel
A D converter, and a digital output signal of each of the A / D converters, which passes through the intersection of the orthogonal axes of the P-channel and Q-channels and π / 4 with respect to the orthogonal axis of the P-channel and the Q-channel.
Two diagonals with radian angle and P channel Q
Only a specific sub-region consisting of 2 ^{N / 2} sub-regions within a square surrounding 2 ^{(N / 2 + 1)} signal points located at the intersection with a circle equidistant from the intersection of the channel axes is identified. A logic circuit that outputs a first detection signal by monitoring the control voltage of the APC for the VCO to determine whether the state is a synchronous state or an asynchronous state, and outputs a second detection signal; The first and second detection signals are input, the second detection signal outputs information indicating an asynchronous state, and the first detection signal outputs information indicating that a transmission signal point exists in the specific sub-region. And a logic circuit that forms the APC when done.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a 16-level quadrature amplitude modulation circuit using a digitized carrier synchronization circuit according to the present invention. In FIG. 1, circuits having the same reference numerals as those of the conventional example shown in FIG. 6 have the same configuration and function. That is, in the embodiment of the present invention, a logic circuit 1, a synchronization determination circuit 2, an AND circuit 3, and an OR circuit 4 are added, and the A / D conversion circuits 18A, 1
9A is improved.

Next, the operation of this embodiment will be described. In this embodiment, as described in [Problems to be Solved by the Invention], the carrier signal phase control is performed to pull the transmission signal point to a true value, but when the phase error is large, the error of the digital output signal becomes large and the loop An object of the present invention is to prevent a decrease in gain and a reduction in a synchronization pull-in range. First, the A / D conversion circuits 18A and 19B
Inputs the analog signals b1 and b2 described above, divides the area segment where the signal point is located into finer divisions than the conventional example, and outputs digital signals of the corresponding areas. A / D
The conversion circuits 18A and 19A add digital output signals c4 and d4, respectively, to specify this new area, and the digital output signals become the Pch digital output signals c1 to c4 and the Qch digital output signals d1 to d4.

Here, the new area division of 16 signal points will be described with reference to the explanatory diagram of the modulation input signal k at the input terminal in FIG. 3 and the explanatory diagram of the A / D converter in FIG. In FIG. 3, S1, S2, S5, S8 of π / 4 radian (45 degrees) with respect to the P axis and the Q axis in the 16 signal point areas.
3 (a) where there is a signal point at the intersection of a diagonal passing through the circle and a diagonal passing through S3, S4, S6, and S7 and a circle (not shown) equidistant from the centers of the P-axis and Q-axis. A total of eight hatch line regions S1 to S8 are set as first determination target regions for performing APC pull-in. That is, taking as an example a region surrounded by the discrimination level (solid line in the figure) of the upper left P1 signal point in FIG. 3 (a), it is divided by three vertical and horizontal dotted lines parallel to the P axis and the Q axis, respectively. The image is divided into 4 × 4 areas, and one of the 16 divided areas is defined as a sub-area. Therefore, S1 to S8 are each composed of four sub-regions centered on the signal point, and these regions are named as specific sub-regions in the claims. Third
The white area around the specific sub-areas S1 to S8 shown in FIG.
However, this area is defined as a first white area. S1 ~ S8
The eight white sub-regions shown in FIG.
In FIG. 3 (b), eight first white regions and eight second white regions are summed up as a second determination target region in FIG. As described above, the first determination target region is divided into the first determination target region and the second determination target region, and the first determination target region is defined as a region where APC pull-in control is performed and the second determination target region is distinguished from asynchronous when there is a phase error. Is divided into cases where the APC voltage is held. Therefore, in the conventional case, the contents described with reference to FIG. 5 will be supplementarily described with reference to FIG. 3 (b).
In the present embodiment, the first white area is excluded in contrast to the APC pull-in performed on the area in which the first white area is added to the S1 to S8 areas provided within the respective signal point identification levels. S1 to S8 regions (only the first determination target region is set as the APC pull-in region. Further, the APC voltage is held for the signal points belonging to the second white region. Since the phase of the oscillation signal of the voltage controlled oscillator 25 is shifted in the direction close to the true value by the APC voltage in the ~ S8 region, the subsequent APC pull-in operation can be shortened. After the transmission signal point is pulled into the true value signal point, the operation returns to the conventional operation of APC control for all signal points, and the synchronous and two asynchronous cases are shown in Tables (a) and (b) below. )
To organize.

The logical operation in Table (b) will be described using a logical circuit including an AND circuit 3 having an inverter and an OR circuit 4.

The logic circuit 1 outputs the output signal e1 (the logic signal “1”) when the transmitted signal point exists in the hatched area for each of the above-mentioned specific sub-areas S1 to S8. ) Is output. If the signal point is outside the hatched area, the output signal e1 is not output. FIG. 2 is a circuit diagram of the logic circuit 1, and the above operation is realized by a combination of an exclusive OR, a logical product, and an inverter.
P1 and Q1 of FIG. 3 represent X1 of FIG. 4, and P2 and Q2 represent X2 of P3 and Q2.
3 represents X3, and P4 and Q4 represent X4. Next, the synchronization determination circuit 2 determines whether the carrier signal of the voltage controlled oscillator 25 is in a synchronized state. Specifically, the input of the voltage controlled oscillator 25
When i2 is monitored and the voltage shifts to a stable fixed voltage, it is regarded as synchronous. When there is a voltage change in a certain range, it is regarded as asynchronous including the first and second asynchronous. The detection signal f is set to “0” level at the time of synchronization, and is set to “1” level at the time of asynchronous. In the AND circuit 3 having the inverter, as shown in Table (b), in the first asynchronous state, e1 inverted by the inverter (after the mark in FIG. 3) is "0" and f is "1".
Therefore, e2 outputs “0”. When e1 becomes "1" in the second asynchronous state and f becomes "1", e2 outputs "1". Second
In the asynchronous state, e1 is "1" and "f" is 1, so e2 outputs "1". On the other hand, the OR circuit 4 outputs the reproduction clock h3
The switch operation is performed in synchronization with the synchronization of, and the output signal e1 is supplied to the flip-flop 11 as the pulse signal h4. That is, when the carrier is asynchronous, the phase control signal obtained only from the range of S1 to S8 is fed back to the voltage controlled oscillator 25. Accordingly, it is possible to reduce errors in the identification result of the base hand signal when the carrier is asynchronous, and to prevent a decrease in loop gain, thereby preventing a decrease in the carrier synchronization pull-in range. However, in this case, since only the eight pieces of information in the S1 to S8 areas, that is, the specific sub-areas, the equivalent clock cycle is doubled because the phase control signal is held at a probability of 1/2. The jitter power is degraded by about 3 dB compared to the case. For this reason, the phase is controlled only at the desired signal point only when the phase error becomes large, such as when the carrier is asynchronous, and it is necessary to switch to all-point control in normal times. In the case of the present embodiment, the case where the switching is performed by the carrier asynchronous signal has been described. However, it is obvious that this can be replaced with another signal such as a signal that detects the deterioration of the error rate. Further, in the present embodiment, only the case of the 16-level quadrature amplitude modulation system is shown, but a general multi-level 2 ^N (N = 2,3,
4 ...) The value quadrature amplitude modulation method can be easily implemented.

〔The invention's effect〕

As described above, the present invention provides a demodulation circuit having a digitized carrier synchronization circuit, a synchronization determination circuit for determining the synchronization of a carrier signal, and an A / D converter for identifying a demodulated quaternary baseband signal. A / D conversion circuit and a logic circuit that logically determines that the error of the digital output signal has become large allow the voltage-controlled oscillator to be controlled only by the phase control signal obtained from the signal point on the specific sub-region. However, phase control information obtained from points other than the desired signal point is stochastic.
Since the phase control signal is held at 1/2, it can be replaced with the held signal. Further, in a normal state in which carrier synchronization is established, the use of phase control signals from all points has the effect of realizing a carrier synchronization circuit having a necessary synchronization pull-in range.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram of a logic circuit 1 which is a main part of the present embodiment, and FIG. 3 is an explanation of a modulation signal k at an input terminal of the present embodiment. FIG. 4 is an operation explanatory diagram of an A / D converter including the present invention and a conventional example.
FIG. 1 is an explanatory diagram showing a signal point arrangement of a general 16-level quadrature amplitude modulation system, and FIG. 6 is a block diagram of a conventional carrier synchronization circuit. DESCRIPTION OF SYMBOLS 1 ... Logic circuit, 2 ... Synchronization judgment circuit, 3 ... AND circuit with inverter, 33,34 ... AND circuit, 4 ... OR circuit, 11 ... Flip-flop, 16,17 ... Multiplier, 18A, 19
A, 18, 19 ... A / D converter, 20, 21, 28 to 32 ... Exclusive OR, 22
... subtractor, 24 ... loop filter, 25 ... voltage controlled oscillator,
26: Clock recovery circuit, 27: π / 2 phase shifter, 35: Inverter.

Claims (1)

(57) [Claims] 1. A carrier generation circuit (hereinafter referred to as VC) used in a multilevel quadrature amplitude modulation system having a multilevel number of 2 ^N (N is an even number of 2 or more).
In carrier synchronization circuit having a synchronization pull-in control loop (hereinafter referred to as APC) of O hereinafter) and the carrier signal of the VCO, the P-channel identification level point of ^the 2 ^N signal points of 2
^{One of} 2 ^N (N is the same as N) divided areas divided into ^{N / 2} and 2 ^{N / 2} areas for the Q channel is defined as a sub-area, and transmission signal points input to the sub-area A / D converters for P-channel and Q-channel for converting an analog signal of the above into a digital signal, and inputting digital output signals of the respective A / D converters, and 2 ^{(N / 2 + 1)} located at the intersection of two diagonals having an angle of π / 4 radian with respect to the orthogonal axis of the channel Q channel and a circle equidistant from the intersection of the P channel Q channel axis A logic circuit that identifies only a specific sub-region consisting of 2 ^{N / 2} sub-regions within a square surrounding the signal point and outputs a first detection signal; and monitors a control voltage of the APC for the VCO. Second detection by determining whether the state is synchronous or asynchronous A synchronization determination circuit that outputs a signal, the first and second detection signals being input, the second detection signal outputting information indicating an asynchronous state, and the first detection signal being transmitted to the specific sub-region. A logic circuit for forming the APC when information indicating that a signal point exists is output.