JP2534650B2 - Demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a demodulation circuit using a carrier regenerating circuit that regenerates a reference carrier from a multilevel quadrature amplitude modulation wave (multilevel QAM modulation wave).

<Prior art> Various microwave digital transmission systems have already been put into practical use, and recently, the multilevel quadrature amplitude modulation system beginning with the 16QAM system has been developed and put to practical use. Such a modulation method enables highly efficient information transmission, but the margin for various external noises is becoming smaller and smaller. Therefore, in the demodulator, the synchronous detection method using the reproduction reference carrier with little noise addition is indispensable.
Furthermore, when reproducing the reference carrier wave, it is necessary to select a circuit configuration in which the jitter component contained in the reference carrier wave is minimized. One of them is the Japanese Patent Application No. 56-015775.
There is a "carrier wave recovery circuit" proposed in Japanese Patent Laid-Open No. 57-131151. This is configured to obtain a phase error signal by logically operating the output data of the multilevel discriminator, and it is possible to obtain a reproduced reference carrier wave with a small jitter component.

<Problems to be Solved by the Invention> However, in order to maintain a high quality reproduction reference carrier, it is necessary to always keep the input level at an optimum value. The characteristics deteriorate significantly. It increases as the multi-valued number of modulated waves increases. Normally, this problem is solved by adding a strict AGC function, but under special conditions this problem cannot be solved. In other words, in the process of establishing synchronization of the carrier recovery circuit, if the AGC function does not operate sufficiently or if there is common-mode interference distortion in the transmission line, it will take a long time to establish the synchronization, or in the worst case, synchronization will not be established. It becomes impossible.

<Means for Solving the Problems> The present invention provides a demodulator having a carrier wave regenerating circuit in which the above-mentioned drawbacks are eliminated. A multi-valued quadrature amplitude modulation wave having 64 or more values is used as a reference carrier wave. Synchronous detection first
And a second demodulated signal, and a carrier synchronization circuit for reproducing the reference carrier by using the phase error signal obtained from the first and second demodulated signals, and constructing the first and second demodulated signals. A demodulator for outputting a signal example of a plurality of data including a main data signal after multi-level identification after level control, wherein the phase error signal is one of the first and second transfer error signals. Phase error signal, the first
The means for obtaining the phase error signal comprises a logic circuit for logically operating the plurality of data signal sequences, and the means for obtaining the second phase error signal outputs π for the first and second demodulated signals, respectively. / 4 radian phase shifting means, first position discriminating means for discriminating the position by binary discrimination of the output of the phase shifting means, and multi-level discrimination of the output of the phase shifting means for 4PSK wave. Using a region discriminating means for discriminating a signal region that can be regarded as equivalent to the signal, and a signal obtained by binary-discriminating the first and second demodulated signals and one of the most significant bits of the main data signal. A logical operation is performed between the second position discriminating means for discriminating the position, the output signals of the first and second position discriminating means, and the output signals of the area discriminating means to obtain the second phase error signal. And a means for making the selection. However, when the level control is normal and the carrier synchronizing circuit is in a stable operation state, the first phase error signal is selected, and when the operation is in transition, the second transfer error signal is selected. Is configured.

<Example> FIG. 1 (a) is a diagram showing a configuration of an example in which the present invention is applied to a 64QAM modulated wave. 1 is a quadrature detector, 2 and 3 are variable attenuators, 4, 5 and 9 to 12 are analog and digital (A / D) converters, 6 and 7 are automatic gain control (AGC) circuits, 8 is carrier wave regeneration Logic circuit for circuit, 13 is subtractor, 14 is adder, 15 is D type flip-flop (FF), 16 is selection circuit, 17 is leaf detection circuit, 1
8 is a reduction filter, 19 is a voltage controlled oscillator, 20 to 24 are exclusive OR (EX-OR) circuits, 25 is an OR circuit, 26 is an AND circuit, 27 is a NAND circuit.
Circuit.

The operation of the above device will now be described. First, a carrier synchronization circuit system used for stable operation will be described. The 64QAM modulated wave which is the input enters the quadrature phase detector 1 and is synchronously detected by the reproduced reference carrier which is the output of the voltage controlled oscillator 19 and converted into demodulated signals P and Q. The variable attenuators 2 and 3 are controlled so that the input levels of the A / D converters 4 and 5 are kept at the optimum levels, and the control signal is the AGC circuit.
Sourced from 6,7. The A / D converters 4 and 5 have 4 bits, the upper 3 bits are used for reproducing the main data signal, and the least significant bit (LSB) is used for the error signal.

Next, the carrier synchronization circuit system used in the operation transition period will be described. A / D converters 9 to 12, subtractor 13, adder 14, EX-
The circuit composed of OR circuits 20, 23, and 24 is a well-known digital Costas type phase synchronization circuit for 4-phase shift keying (4PSK) waves, and was announced at the nationwide conference of the Institute of Electronics and Communication Engineers in 1977, for example. No. 1845 "4PSK demodulator using a baseband processing type carrier synchronization circuit" is also described.
Subtracter 13, the adder 14 is for each [pi / 4 radians phase demodulation signal P, Q, and the output L ₁ was identified 2 values by the A / D converter 11 and 12 EX-OR circuit 23 The phase discrimination signal S ₁ is obtained by the EX-OR operation. One-way demodulated signals P and Q
Of the two signals, which are binary-coded by the A / D converters 9 and 10, or A
The EX-OR circuit outputs the main data signal D ₁
Perform EX-OR operation at 20 and output. It goes without saying that the above two D ₁ outputs are equivalent to the outputs of the A / D converters 9 and 10 for this purpose. Then the same as the EX-OR circuit 23
If you use the EX-OR circuit 24 to perform an EX-OR operation on the output of 20 and EX-O
The output of the R circuit 24 becomes the phase error signal for the 4PSK wave.

Referring to FIG. 2 (a), the phase error signal obtained from the EX-OR circuit 24 is a signal that can be regarded as equivalent to a 4PSK wave, that is, a P ₁ axis that is π / 4 radian-shifted from the P ₀ and Q ₀ axes, Q Obtained from the signal points on the _1st axis. At that time, it is irrelevant to the amplitude value of each signal point, and if it is on the P ₁ and Q ₁ axes, a wrong phase error signal is not created, and the correct phase error information is obtained only when it is separated from the P ₁ and Q ₁ axes. Becomes This means that this phase locked loop is resistant to level fluctuations. However, the input signal is now a 64QAM modulated wave, and there are many signal points on the P ₁ and Q ₁ axes, and these signal points are far from the P ₁ Q ₁ axis, and correct phase error information is obtained from these. Not only can you not give out,
Since will undergo jitter Conversely, by providing a region in the vicinity of P _1, Q ₁ axis, only when the signal points are entered this area EX-OR circuit
It is configured to use 24 outputs.

The threshold level of the L ₂ output of the A / D converters 11 and 12 is set to ± l in Fig. 2 (a), and the EX-OR circuit 2
The output of 1, 22 has a respective signal point at a time other than the region a _1, a "0".
The NAND circuit 27 receives these two signals and receives the area determination signal S ₂
Occurs. Therefore, when each signal point enters the area a _{1 at} the output of the AND circuit 26, the CLK signal is transmitted and the D-type flip-flop FF15 reads the output of the EX-OR circuit 24. By the above operation, the phase error information is extracted from the signal points near the P ₁ and Q ₁ axes, so that the reference carrier with less jitter component can be regenerated.

The smaller the set value of the threshold level ± l is, the smaller the jitter component becomes, but at that time, the pull-in phase is not in the state shown in FIG. 2 (a) but is stable at a position having a certain phase rotation from this state. Since a so-called pseudo-pull-in phenomenon occurs, it can be said that it is desirable to set the value of l to the maximum value that does not include other signal points on the P ₁ and Q ₁ axes.

FIG. 1 (b) is a diagram showing a configuration example of another area determination circuit that can generate the area determination signal S ₂ by a method other than that shown in FIG. 1 (a), and 28 is a read only memory (ROM). Is. In FIG. 2 (b), it is sufficient to write in the ROM so that when the signal point enters the area a ₂ , "1" is sent to the output of the ROM 28.

The carrier synchronization circuit used in the above-mentioned operation transition period has the advantage that it does not depend on the input level, but since it detects an error signal from a part of the signal points of the input modulated wave, The included jitter component is slightly larger than that of the conventional carrier synchronization circuit. Therefore, in the stable state where the carrier wave synchronization circuit is established, it is better to use the conventional carrier wave synchronization circuit, and this becomes more effective as the number of multivalues increases.

The selection circuit 16 in FIG. 1 (a) switches between both, and the alarm signal ALM from the AGC circuits 6 and 7 and the detection circuit 17 is selected.
Disappears, that is, when the present demodulator enters stable operation from the transitional period of operation, the phase error signal output from the logic circuit 8 is selected by the selection circuit 16 and sent to the voltage controlled oscillator 19 via the reduction wave filter 18. Is entered.

Logic circuit 8 of carrier synchronization circuit used in steady operation
The operation of is described in detail in the above-mentioned Japanese Patent Application No. 56-015775, so it will be omitted here.

FIG. 3 (a) is a concrete example of the AGC circuits 6 and 7, and FIG.
Is an operation explanatory diagram thereof, 29 is a logic circuit, 30 is a flip-flop (FF), and 31 is a detection circuit. The output S of the logic circuit 29 outputs "1" when the signal point enters the area C ₀ in FIG. 3 (b), and the output R outputs "1" when the signal point enters the area C ₁ . Print the output. These outputs are flip-flops FF
It becomes a control signal of the variable attenuators 2 and 3 of FIG. Here, when the AGC circuit is not operating normally, that is, when the signal point enters only _one of the areas C _{0 and} C ₁ , the output of FF30 becomes DC level. or,
In the normal state, the data signal has a mark rate of 1/2. Therefore, the difference between the two is detected by the detection circuit 31, and the ALM signal is transmitted in the event of an abnormality.

Returning to FIG. 1, the carrier wave synchronizing circuit based on the output of the flip-flop FF15 is established independently of the input level, but the carrier wave synchronizing circuit based on the output of the logic circuit 8 depends on the input level. It is indispensable to confirm whether the AGC circuit is operating normally when switching from the output of the logic circuit 8 to the output of the logic circuit 8 (phase error signal). In addition to the output ALM of the carrier synchronization circuit alarm, that is, the detection period 17, the ALM signals of AGC6 and 7 are used to determine whether the operation is in transition or stable. Note that the CONT signal of the selection circuit 16 can use information from the code error rate characteristic other than the above.

The case where the present invention is applied to a 64QAM system has been described above with reference to FIG. 1, but the present invention is not limited to this and can be applied to a multilevel quadrature amplitude modulation system of 4QAM (4PSK) or more. . When changing FIG. 1 to a system other than the 64QAM system, only the number of bits of the A / D converters 4 and 5 and the storage capacity of the read only memory (ROM) 28 need be changed.

<Effects of the Invention> As can be seen from the above description, according to the present invention, a carrier wave synchronizing circuit that does not depend on the input level can be configured even if the input signal is a multilevel quadrature amplitude modulated wave, and the common mode interference in the transmission system is achieved. It has the advantages that synchronization cannot be established even if there is distortion, and the establishment speed is fast.

[Brief description of drawings]

FIG. 1 (a) is a diagram showing a configuration of an embodiment in which the present invention is applied to a 64QAM modulated wave, FIG. 1 (b) is a diagram showing a configuration of another embodiment of the area determination circuit, and FIG. 2 (a). ) Is a diagram showing a signal arrangement of a 64QAM modulated wave, FIG. 2 (b) is an operation explanatory diagram of FIG. 2 (a), and FIG. 3 (a) is a diagram showing a configuration of a specific example of an AGC circuit. FIG. 3B is an operation explanatory view of FIG. 3A. Explanation of symbols: 1 is a quadrature detector, 2 to 3 are variable attenuators, 4 to
5, 9 to 12 are A / D converters, 6 to 7 are AGC, 8 is a logic circuit, 13 is a subtractor, 14 is an adder, 15 is a FF, 16 is a selection circuit, 17 is a detection circuit, and 18 is Low-pass 3-wave device, 19 is voltage controlled oscillator, 20 to 24 is EX
-OR circuit, 25 OR circuit, 26 AND circuit, 27 NAND circuit, 28 R
OM, 29 is a logic circuit, 30 is an FF, and 31 is a detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Manabu Yagi 5-33-1 Shiba, Minato-ku, Tokyo NEC Electric Co., Ltd. (72) Toru Matsuura 5-33-1-3 Shiba, Minato-ku, Tokyo NEC Incorporated (56) References JP 57-131151 (JP, A) JP 60-162337 (JP, A) Proceedings of the 50th National Conference of the Institute of Electronics and Communication Engineers [Separate Volume 8] Paper No. 1819 Research Institute of Communications Research Vol. 30, No. 6 (1981) PP. 1415-1427

Claims (1)

(57) [Claims] 1. A multi-valued quadrature amplitude modulation wave having 64 or more values is synchronously detected with a reference carrier to obtain first and second demodulated signals, and the first and second demodulated signals are obtained. A carrier wave synchronizing circuit for reproducing the reference carrier wave by using a phase error signal is configured, and the first and second demodulated signals are level-controlled and then multivalued to output a plurality of data signal examples including a main data signal. In the demodulator, the phase error signal is one of the phase error signals selected from the first and second phase error signals, and the means for obtaining the first phase error signal outputs the plurality of data signal sequences. And a means for obtaining the second phase error signal, the means for obtaining the second phase error signal and the phase shift means for respectively shifting the first and second demodulated signals by π / 4 radians, and this phase shift The position is discriminated by binary-identifying the output of the means. A first position determining means, and area discrimination means for performing the multi-level decision discrimination of 4PSK wave to be equivalent regarded signal area by performing the output of said phase shifting means, said first and second
Second position discriminating means for discriminating the position by using one of the signal obtained by binary-discriminating the demodulated signal and the most significant bit of the main data signal, and the first and second position discriminating means. Means for performing a logical operation between the output signal of the means and the output signal of the area discriminating means to obtain the second phase error signal, and the means for performing the selection is the level control. Is normal and the carrier synchronization circuit is in a stable operation state, the first phase error signal is selected, and when the operation is in transition, the second phase error signal is selected. Demodulating device.