JP2587432B2 - Effective area judgment signal detection circuit - Google Patents

Effective area judgment signal detection circuit

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Publication number
JP2587432B2
JP2587432B2 JP62274938A JP27493887A JP2587432B2 JP 2587432 B2 JP2587432 B2 JP 2587432B2 JP 62274938 A JP62274938 A JP 62274938A JP 27493887 A JP27493887 A JP 27493887A JP 2587432 B2 JP2587432 B2 JP 2587432B2
Authority
JP
Japan
Prior art keywords
signal
circuit
discriminating
effective area
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62274938A
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Japanese (ja)
Other versions
JPH01117450A (en
Inventor
祥一 溝口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62274938A priority Critical patent/JP2587432B2/en
Priority to CA000581582A priority patent/CA1273069A/en
Priority to US07/264,150 priority patent/US4859956A/en
Priority to AU24548/88A priority patent/AU601665B2/en
Priority to DE88118159T priority patent/DE3882484T2/en
Priority to EP88118159A priority patent/EP0314196B1/en
Publication of JPH01117450A publication Critical patent/JPH01117450A/en
Application granted granted Critical
Publication of JP2587432B2 publication Critical patent/JP2587432B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は有効領域判定信号検出回路に係り、特に、位
相平面上の信号点配置が階段状となるようにする高多値
直交振幅変調方式を採用するディジタル無線通信システ
ムにおける復調装置において用いられる有効領域判定信
号検出回路に関する。
Description: BACKGROUND OF THE INVENTION The present invention relates to an effective area determination signal detection circuit, and in particular, to a high multi-level quadrature amplitude modulation system in which a signal point arrangement on a phase plane is stepped. The present invention relates to an effective area determination signal detection circuit used in a demodulation device in a digital wireless communication system adopting the above.

(従来の技術) 周知のように、ディジタル無線通信においては、周波
数有効利用の観点から高多値の直交振幅変調(QAM)方
式が採用されている。これには、64QAM方式や256QAM方
式等の各種のものがある。しかし、このQAM方式は、例
えば第5図に示す如く、位相平面上の信号点配置態様が
正方形となるので、高多値になるに従い変調波のピーク
電力対平均電力比が大きくなり、送信電力増幅器等の非
線形歪を受け易くなる。
(Prior Art) As is well known, in digital wireless communication, a high-valued quadrature amplitude modulation (QAM) method is adopted from the viewpoint of effective frequency utilization. This includes various types such as the 64QAM system and the 256QAM system. However, in this QAM system, as shown in FIG. 5, for example, the signal point arrangement on the phase plane is square, so that the peak power-to-average power ratio of the modulated wave increases as the number of values increases, and the transmission power increases. It becomes susceptible to non-linear distortion of an amplifier or the like.

そこで、例えば第6図に示す如く、位相平面上の信号
点配置が階段状となるようにし、以てピーク電力の低減
を図るようにした直交振幅変調方式(STEPPED−SQUARE
QAM方式:以下、単に「SS−QAM」方式という)が提案さ
れている(特開昭61−77452号公報)。第6図は256SS−
QAM方式の信号点配置を示し、最外殻信号点を結ぶ外形
状は正8角形となっており、通常のQAM方式の正方形各
頂点付近の信号点を削除した形状となっている。
Therefore, for example, as shown in FIG. 6, a quadrature amplitude modulation scheme (STEPPED-SQUARE) in which the signal points on the phase plane are arranged in a step-like manner to reduce the peak power.
QAM system: hereinafter, simply referred to as “SS-QAM” system) (Japanese Patent Laid-Open No. 61-77452). Fig. 6 shows 256SS-
The signal point arrangement of the QAM method is shown. The outer shape connecting the outermost signal points is a regular octagon, and the signal points near the vertices of each square of the normal QAM method are deleted.

ところで、QAM変調波を正しく復調するためには自動
振幅制御信号(AGC)、搬送波再生信号、DCオフセット
制御信号および伝搬路でのフェージング歪等を等化する
トランスバーサル形等化器のタップ制御信号等を生成す
るために、理想値からの信号点のずれを表す誤差信号が
必要となるが、復調装置の制御ループが正しく引き込ま
ない間は、信号レベルの最も大きい信号点位置の外側の
みを用いる最大レベル誤差法(MLE)によって有効な誤
差信号を得るようにしている。即ち、第7図は第5図と
同様の256QAM方式の信号点配置を示すが、最外殻の信号
点位置を結ぶ正方形領域の外側部分(図中斜線部分)を
有効領域とし、この有効領域に信号が入った時に得られ
た誤差信号のみを有効なものとして各種制御に用い、他
は放棄する方法である。
By the way, in order to correctly demodulate a QAM modulated wave, an automatic amplitude control signal (AGC), a carrier recovery signal, a DC offset control signal, and a tap control signal of a transversal equalizer for equalizing fading distortion and the like in a propagation path. An error signal indicating the deviation of the signal point from the ideal value is required to generate the like, but only the outside of the position of the signal point having the highest signal level is used while the control loop of the demodulator is not correctly pulled in. An effective error signal is obtained by a maximum level error method (MLE). That is, FIG. 7 shows the signal point constellation of the 256QAM system similar to that of FIG. 5, but the outer part (shaded area in the figure) of the square area connecting the signal point positions of the outermost shell is defined as an effective area. In this method, only an error signal obtained when a signal is input to the controller is used for various controls as an effective signal, and the others are discarded.

要するに、QAM方式では、信号が有効領域に入ったこ
とを示す信号、即ち有効領域判定信号を如何に検出する
かが問題となるが、256SS−QAM方式における従来の有効
領域判定方式は次の如くして行われている。第8図は従
来の有効領域判定信号検出回路を示す。第8図におい
て、21,22はA/D変換器、23は信号変換回路である。
In short, in the QAM method, a signal indicating that a signal has entered an effective area, that is, how to detect an effective area determination signal is a problem. However, the conventional effective area determination method in the 256SS-QAM method is as follows. It has been done. FIG. 8 shows a conventional effective area determination signal detection circuit. In FIG. 8, reference numerals 21 and 22 denote A / D converters, and reference numeral 23 denotes a signal conversion circuit.

図外の復調装置で取得された互いに直交関係にあるP
チャネルとQチャネルのベースバンド信号はそれぞれ入
力端子51,同52を介してA/D変換器21,同22へ入力する。
また、入力端子53に印加されるクロック信号はA/D変換
器21,同22および信号変換回路23へ識別タイミングを決
定する動作クロックとして与えられる。
P that are orthogonal to each other and obtained by a demodulation device (not shown)
The baseband signals of the channel and the Q channel are input to A / D converters 21 and 22 via input terminals 51 and 52, respectively.
The clock signal applied to the input terminal 53 is supplied to the A / D converters 21, 22 and the signal conversion circuit 23 as an operation clock for determining the identification timing.

A/D変換器21,同22は、入力したベースバンド信号を5
ビットのデータ信号と1ビットの誤差信号へ変換し、そ
れを信号変換回路23へ与える。第6図から明らかなよう
に、256SS−QAM方式では、Pチャネル、Qチャネルとも
に18値のレベルを持っているので、データ信号は5ビッ
ト必要なのである。
A / D converters 21 and 22 convert the input baseband signal into 5
The signal is converted into a 1-bit data signal and a 1-bit error signal, and is supplied to a signal conversion circuit 23. As is apparent from FIG. 6, in the 256SS-QAM system, since the P channel and the Q channel have 18 levels, the data signal needs 5 bits.

信号変換回路23は、論理ゲートを複数用いた個別論理
回路ないしはROM等で構成され、PチャネルとQチャネ
ルの合計10ビットのデータ信号を用いて最外殻信号点位
置(第9図中黒丸(・)で示す)の24個の信号a〜同x
の受信を検出し、それを第9図中3角形印(△)で示す
24個の信号点位置の信号a′〜同x′に変換する。即
ち、等価的に第5図に示した如き正方形信号点配置にお
いて信号を受信したとみなし、通常のQAM方式(第7
図)と同様に、10ビットのデータ信号と2ビットの誤差
信号とから有効領域に信号が入ったことを検出し、出力
端子54を“1"にして有効領域判定信号を出力するように
なっている。
The signal conversion circuit 23 is composed of an individual logic circuit using a plurality of logic gates or a ROM or the like, and uses the data signal of a total of 10 bits of the P channel and the Q channel to determine the position of the outermost shell signal point (the black circle in FIG. 9). 24) a to x
9 is detected, and this is indicated by a triangle (△) in FIG.
The signals are converted into signals a 'to x' of 24 signal point positions. That is, it is assumed that the signal is received equivalently in the square signal point constellation as shown in FIG.
In the same manner as in FIG. 3, it is detected that a signal has entered the effective area from the 10-bit data signal and the 2-bit error signal, and the output terminal 54 is set to “1” to output an effective area determination signal. ing.

(発明が解決しようとする問題点) しかしながら、SS−QAM方式における従来の有効領域
判定信号検出方式にあっては、前述した通り一度通常の
QAM方式の信号点配置へ変換する方式であり、この変換
は制御ループの引き込みが不確定または引き込んでいて
も誤り率の非常に大きい段階で行われるため、正しい変
換が行われない。故に、正しい有効領域判定信号が検出
できず、復調動作が著しく不安定になるという問題点が
ある。
(Problems to be Solved by the Invention) However, in the conventional effective area determination signal detection method in the SS-QAM method, once a normal
This is a method of converting to the signal point arrangement of the QAM method. This conversion is performed at a stage where the error rate is extremely large even if the control loop pull-in is uncertain or pull-in, so that correct conversion is not performed. Therefore, there is a problem that a correct valid area determination signal cannot be detected and the demodulation operation becomes extremely unstable.

本発明は、このような従来の問題点に鑑みなされたも
ので、その目的は、SS−QAM方式下における復調システ
ムにおいて、正しい有効領域判定信号の検出が行え、以
て復調動作の安定化を可能にする有効領域判定信号検出
回路を提供することにある。
The present invention has been made in view of such a conventional problem, and an object of the present invention is to perform a correct detection of an effective area determination signal in a demodulation system under the SS-QAM scheme, thereby stabilizing a demodulation operation. An object of the present invention is to provide an effective area determination signal detection circuit which enables the detection.

(問題点を解決するための手段) 前記目的を達成するために、本発明の有効領域判定信
号検出回路は次の如き構成を有する。
(Means for Solving the Problems) In order to achieve the above object, an effective area determination signal detection circuit of the present invention has the following configuration.

即ち、本発明の有効領域判定信号検出回路は、位相平
面上の信号点配置が階段状となるようにする高多値直交
振幅変調方式を採用するデジタル無線通信システムにお
ける復調装置において用いられる上記信号点配置の最外
殻信号点位置の外側部分を有効領域として検出する有効
領域判定信号検出回路であって; この有効領域判定信号検出回路は、復調装置において
取得された互いに直交関係にあるPチャネルとQチャネ
ルの各ベースバンド信号間で加算処理を行う信号加算回
路と; PチャネルとQチャネルの各ベースバンド信号間で減
算処理を行う信号減算回路と; 信号加算回路の出力を受けて(P+Q)軸の最外殻信
号点位置の外側部分で信号検出をなしたことを判定して
信号点識別を行う第1の信号識別回路と; 信号減算回路の出力を受けて(P−Q)軸の最外殻信
号点位置の外側部分で信号検出をなしたことを判定して
信号点識別を行う第2の信号識別回路と; PチャネルとQチャネルの各ベースバンド信号のそれ
ぞれについてP軸またはQ軸の最外殻信号点位置の外側
部分で信号検出をなしたことを判定して信号点識別を行
う第3および第4の信号識別回路と; 前記第1乃至第4の識別回路の各出力間で論理和処理
をし有効領域判定信号を出力する論理和回路と; を備えたことを特徴とするものである。
That is, the effective area determination signal detection circuit according to the present invention is a signal processing method for use in a demodulation device in a digital wireless communication system employing a high multi-level quadrature amplitude modulation scheme in which signal point arrangement on a phase plane is stepped. An effective area determination signal detection circuit for detecting an outer part of the position of the outermost signal point of the point arrangement as an effective area; the effective area determination signal detection circuit includes P-channels orthogonal to each other and acquired by a demodulator. And a signal addition circuit for performing an addition process between the baseband signals of the Q and Q channels; a signal subtraction circuit for performing a subtraction process between the baseband signals of the P and Q channels; and receiving the output of the signal addition circuit (P + Q A) a first signal discriminating circuit for discriminating that a signal has been detected outside the outermost signal point position of the axis and discriminating a signal point; A second signal discriminating circuit for discriminating that a signal has been detected in a portion outside the outermost signal point position of the (P-Q) axis and discriminating a signal point; each base of a P channel and a Q channel; A third and a fourth signal discriminating circuit for discriminating that a signal has been detected in a portion outside the position of the outermost signal point on the P axis or the Q axis for each of the band signals and discriminating the signal points; A logical sum circuit that performs a logical sum process between the outputs of the fourth to fourth identification circuits and outputs an effective area determination signal.

(作 用) 次に、前記の如く構成される本発明の有効領域判定信
号検出回路の作用を第1図を参照して説明する。
(Operation) Next, the operation of the effective area determination signal detection circuit of the present invention configured as described above will be described with reference to FIG.

第1図は前述した256SS−QAM方式の信号点配置を示す
が、本発明においては有効領域判定信号を従来の如く通
常のQAM方式の信号点配置へ変換することなく直接的に
検出しようとするものである。
FIG. 1 shows the signal point constellation of the 256SS-QAM method described above. In the present invention, the effective area determination signal is directly detected without being converted to the signal point constellation of the normal QAM method as in the related art. Things.

即ち、信号加算回路の出力は各信号点位置の軸(P+
Q)への正射影となり、信号減算回路の出力は各信号点
位置の軸(P−Q)への正射影となるから、軸(P+
Q)および軸(P−Q)上の25値の信号レベルを第1お
よび第2の信号識別回路において識別することによっ
て、正方形の判定領域(I)の外側で信号が受信された
のを検出できる。また、軸Pおよび軸Q上の18値の信号
レベルを第3および第4の信号識別回路において識別す
ることによって、正方形の判定領域(II)の外側で信号
が受信されたのを検出できる。故に、論理和回路の出力
には、最外殻信号点位置の外側で信号受信が行われたこ
とを示す信号、即ち有効領域判定信号が得られる。
That is, the output of the signal addition circuit is the axis (P +
Q), and the output of the signal subtraction circuit is an orthogonal projection to the axis (PQ) of each signal point position.
Q) and the 25 signal levels on the axis (PQ) are identified in the first and second signal identification circuits to detect that a signal has been received outside the square decision area (I). it can. Further, by identifying the 18 signal levels on the axes P and Q in the third and fourth signal discriminating circuits, it is possible to detect that a signal has been received outside the square determination area (II). Therefore, a signal indicating that the signal has been received outside the position of the outermost signal point, that is, an effective area determination signal is obtained from the output of the OR circuit.

このように、本発明の有効領域判定信号検出回路によ
れば、SS−QAM方式の信号点配置の最外殻信号点位置の
外側部分(有効領域)で信号受信の行われたことを示す
有効領域判定信号を従来の如く通常のQAM方式の信号点
配置(正方形)へ変換することなく直接的に得ることが
できるので、復調装置の制御ループの引き込みが不確定
ないしは引き込んでいても誤り率が非常に大きい段階で
も正しい有効領域判定信号を検出でき、復調動作の安定
化を可能にする効果がある。
As described above, according to the effective area determination signal detection circuit of the present invention, the effective area indicating that the signal has been received in the outer part (effective area) of the outermost signal point position of the signal point constellation of the SS-QAM scheme. Since the area determination signal can be obtained directly without converting to the signal point constellation (square) of the normal QAM system as in the conventional case, the error rate is not affected even if the control loop of the demodulation device is uncertain or pulled in. Even in a very large stage, a correct effective area determination signal can be detected, and the demodulation operation can be stabilized.

(実 施 例) 以下、本発明の実施例を図面を参照して説明する。Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第2図は本発明の一実施例に係る有効領域判定信号検
出回路を示す。第2図において、11は信号加算回路、12
は信号減算回路、13〜16は信号識別回路、17は4入力の
論理和回路である。
FIG. 2 shows an effective area determination signal detection circuit according to one embodiment of the present invention. In FIG. 2, reference numeral 11 denotes a signal addition circuit;
Is a signal subtraction circuit, 13 to 16 are signal identification circuits, and 17 is a 4-input OR circuit.

入力端子1に印加されるPチャネルのベースバンド信
号は信号加算回路11および信号減算回路12それぞれの一
方の入力と信号識別回路15へ与えられる。また、入力端
子2に印加されるQチャネルのベースバンド信号は信号
加算回路11および信号減算回路12それぞれの他方の入力
と信号識別回路16へ与えられる。さらに、入力端子3に
印加されるクロック信号は信号識別回路13〜同16へ識別
タイミングを規定する動作クロックとして与えられる。
The P-channel baseband signal applied to the input terminal 1 is supplied to one input of each of a signal addition circuit 11 and a signal subtraction circuit 12 and to a signal identification circuit 15. The Q channel baseband signal applied to the input terminal 2 is supplied to the other input of the signal addition circuit 11 and the other input of the signal subtraction circuit 12, and to the signal identification circuit 16. Further, the clock signal applied to the input terminal 3 is supplied to the signal identification circuits 13 to 16 as an operation clock for defining the identification timing.

256SS−QAM方式の信号点配置は、第6図に示した如く
であって、最外殻信号点を結ぶ外周形状は正8角形とな
っている。本発明においては、正8角形の各辺に位置す
る信号点を直接検出できるようにしようとするものであ
る。即ち、互いに直交する2つ軸Pと同Qはそれぞれ対
向する1対の辺について規定できるから、残る2対の辺
について規定できる軸(P+Q)と軸(P−Q)を第3
図に示す如く軸Pから45度傾斜した位置に直交配置し、
斯く設定した4つの軸P,同Q,同(P+Q),同(P−
Q)上で信号点位置識別をなし、以て正8角形の各周の
外側部分(有効領域)の判定を直接的に行えるようにし
ようとするものである。
The signal point arrangement of the 256SS-QAM system is as shown in FIG. 6, and the outer peripheral shape connecting the outermost signal points is a regular octagon. The present invention is intended to directly detect signal points located on each side of a regular octagon. That is, since the two axes P and Q orthogonal to each other can be defined for a pair of opposing sides, the axis (P + Q) and the axis (P-Q) that can be defined for the remaining two pairs of sides are the third.
As shown in the figure, it is arranged orthogonally at a position inclined 45 degrees from the axis P,
The four axes P, Q, (P + Q) and (P-
Q) The signal point position is identified above, so that the outer portion (effective area) of each circumference of the regular octagon can be directly determined.

信号加算回路11は、PチャネルとQチャネルの各ベー
スバンド信号間で加算処理をしその結果出力5を信号識
別回路13へ与える。結果出力5は、各信号点位置の軸P
+Qへの正射影となり、これは25値の信号レベルとな
る。
The signal addition circuit 11 performs an addition process between the baseband signals of the P channel and the Q channel, and provides an output 5 to the signal identification circuit 13 as a result. The result output 5 is the axis P of each signal point position.
+ Q, which is a 25-level signal level.

信号減算回路12は、PチャネルとQチャネルの各ベー
スバンド信号間で減算処理をしその結果出力6を信号識
別回路14へ与える。結果出力6は、各信号点位置の軸P
−Qへの正射影となり、これは25値の信号レベルとな
る。
The signal subtraction circuit 12 performs a subtraction process between the baseband signals of the P channel and the Q channel, and outputs the result 6 to the signal identification circuit 14. The result output 6 is the axis P of each signal point position.
This is an orthogonal projection to -Q, which is a signal level of 25 values.

信号識別回路13,同14では、第4図(a)に示す如
く、入力する25値の信号レベルの各レベルにおけるアイ
パターンから各信号レベルの信号点位置を識別し、最外
殻信号点位置の外側部分で信号検出をなした場合には判
定出力を“1"レベルにし、他の場合には“0"レベルにす
る。この判定出力7,同8は論理和回路17へ与えられる。
As shown in FIG. 4 (a), the signal discriminating circuits 13 and 14 discriminate the signal point positions of each signal level from the eye pattern at each of the input 25-value signal levels, and If the signal is detected in the outer part of, the determination output is set to the “1” level, otherwise, it is set to the “0” level. The judgment outputs 7 and 8 are supplied to the OR circuit 17.

一方、信号識別回路15,同16では、第4図(b)に示
す如く、入力する18値の信号レベルの各レベルにおける
アイパターンから各信号レベルの信号点位置を識別し、
最外殻信号点位置の外側部分で信号検出をなした場合に
は判定出力を“1"レベルにし、他の場合には“0"レベル
にする。この判定出力9,同10は論理和回路17へ与えられ
る。
On the other hand, the signal discriminating circuits 15 and 16 discriminate the signal point positions of each signal level from the eye pattern at each of the 18 input signal levels, as shown in FIG.
When a signal is detected outside the position of the outermost signal point, the determination output is set to “1” level, and otherwise, the determination output is set to “0” level. The judgment outputs 9 and 10 are given to the OR circuit 17.

斯くして、論理和回路17では、4個の判定出力7,同8,
同9,同10の論理和がとられ、出力端子4へ有効領域判定
信号Vが送出される。
Thus, in the OR circuit 17, the four judgment outputs 7, 8, and
The logical sum of the same 9 and 10 is obtained, and the effective area determination signal V is sent to the output terminal 4.

この論理和回路17は、256SS−QAM方式のような多値数
の大きい変調方式では、信号点が有効領域に入る確率が
低くなるので、なるべく多くの有効な誤差信号情報を得
るために設けてある。即ち、この論理和回路17によって
有効領域に入った信号点の誤差信号情報は、全てPチャ
ネル及びQチャネルのAGC、APC、DCオフセット制御信
号、タップ制御信号等を生成するために用いられる。
The OR circuit 17 is provided in order to obtain as much effective error signal information as possible, since the probability that a signal point enters an effective area is reduced in a modulation scheme having a large number of values such as the 256SS-QAM scheme. is there. That is, the error signal information of the signal points entering the effective area by the OR circuit 17 is used for generating AGC, APC, DC offset control signal, tap control signal, etc. of P channel and Q channel.

ここに、有効領域判定信号Vは、受信された信号が第
1図に示す正方形領域(I)または同(II)の外側にあ
るとき、即ち第1図中斜線部分で信号が受信された場合
にのみ“1"レベルとなり、有効領域検出を報知すること
になる。
Here, the valid area determination signal V is obtained when the received signal is outside the square area (I) or (II) shown in FIG. 1, that is, when the signal is received in the shaded area in FIG. Only at the “1” level, and the effective area detection is notified.

(発明の効果) 以上説明したように、本発明の有効領域判定信号検出
回路によれば、SS−QAM方式の信号点配置の最外殻信号
点位置の外側部分(有効領域)で信号受信の行われたこ
とを示す有効領域判定信号を従来の如く通常のQAM方式
の信号点配置(正方形)へ変換することなく直接的に得
ることができるので、復調装置の制御ループの引き込み
が不確定ないしは引き込んでいても誤り率が非常に大き
い段階でも正しい有効領域判定信号を検出でき、復調動
作の安定化を可能にする効果がある。
(Effect of the Invention) As described above, according to the effective area determination signal detection circuit of the present invention, signal reception is performed in an outer part (effective area) of the outermost signal point position of the SS-QAM signal point arrangement. Since the effective area determination signal indicating that the operation has been performed can be directly obtained without converting the signal point constellation (square) of the ordinary QAM method as in the related art, the control loop of the demodulation device is uncertain or uncertain. Even if the error rate is drawn, the correct valid area determination signal can be detected even at a stage where the error rate is extremely large, and there is an effect that the demodulation operation can be stabilized.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の有効領域判定信号検出の原理説明図、
第2図は本発明の一実施例に係る有効領域判定信号検出
回路の構成ブロック図、第3図はP軸−Q軸と(P+
Q)軸−(P−Q)軸の関係図、第4図は信号識別回路
の動作説明図、第5図は256QAM方式の信号点配置図、第
6図は256SS−QAM方式の信号点配置図、第7図は256QAM
方式における有効領域判定方式の説明図、第8図は従来
の有効領域判定信号検出回路の構成ブロック図、第9図
は従来の有効領域判定の動作説明図である。 11……信号加算回路、12……信号減算回路、13〜16……
信号識別回路、17……論理和回路、21,22……A/D変換
器、23……信号変換回路。
FIG. 1 is a diagram for explaining the principle of detection of an effective area determination signal according to the present invention;
FIG. 2 is a block diagram showing a configuration of an effective area determination signal detection circuit according to one embodiment of the present invention, and FIG. 3 is a diagram showing P axis-Q axis and (P +
Q) Axis- (PQ) axis relationship diagram, FIG. 4 is an explanatory diagram of the operation of the signal identification circuit, FIG. 5 is a signal point arrangement diagram of the 256QAM system, and FIG. 6 is a signal point arrangement of the 256SS-QAM system. Figure 7 is 256QAM
FIG. 8 is an explanatory diagram of an effective area determination method in the system, FIG. 8 is a block diagram of a configuration of a conventional effective area determination signal detection circuit, and FIG. 9 is an operation explanatory view of a conventional effective area determination. 11 ... Signal addition circuit, 12 ... Signal subtraction circuit, 13-16 ...
Signal discriminating circuit, 17… OR circuit, 21, 22… A / D converter, 23 …… Signal converting circuit.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】位相平面上の信号点配置が階段状となるよ
うにする高多値直交振幅変調方式を採用するデジタル無
線通信システムにおける復調装置において用いられる上
記信号点配置の最外殻信号点位置の外側部分を有効領域
として検出する有効領域判定信号検出回路であって; この有効領域判定信号検出回路は、復調装置において取
得された互いに直交関係にあるPチャネルとQチャネル
の各ベースバンド信号間で加算処理を行う信号加算回路
と; PチャネルとQチャネルの各ベースバンド信号間で減算
処理を行う信号減算回路と; 信号加算回路の出力を受けて(P+Q)軸の最外殻信号
点位置の外側部分で信号検出をなしたことを判定して信
号点識別を行う第1の信号識別回路と; 信号減算回路の出力を受けて(P−Q)軸の最外殻信号
点位置の外側部分で信号検出をなしたことを判定して信
号点識別を行う第2の信号識別回路と; PチャネルとQチャネルの各ベースバンド信号のそれぞ
れについてP軸またはQ軸の最外殻信号点位置の外側部
分で信号検出をなしたことを判定して信号点識別を行う
第3および第4の信号識別回路と; 前記第1乃至第4の識別回路の各出力間で論理和処理を
し有効領域判定信号を出力する論理和回路と; を備えたことを特徴とする有効領域判定信号検出回路。
1. An outermost signal point of said signal point arrangement used in a demodulator in a digital radio communication system employing a high multi-level quadrature amplitude modulation system in which a signal point arrangement on a phase plane is stepped. An effective area determination signal detection circuit for detecting an outer part of the position as an effective area; the effective area determination signal detection circuit detects baseband signals of a P channel and a Q channel which are orthogonal to each other and acquired by a demodulation device. A signal addition circuit for performing an addition process between the signals; a signal subtraction circuit for performing a subtraction process between each baseband signal of the P channel and the Q channel; an outermost signal point on the (P + Q) axis receiving an output of the signal addition circuit A first signal discriminating circuit for discriminating that a signal has been detected at a position outside the position and discriminating a signal point; and receiving an output of the signal subtracting circuit, an outermost shell signal on the (PQ) axis A second signal discriminating circuit for discriminating that a signal has been detected in a portion outside the point position and discriminating a signal point; an outermost P-axis or Q-axis for each of the baseband signals of the P channel and the Q channel; A third and a fourth signal discriminating circuit for discriminating that a signal has been detected outside the shell signal point position and discriminating a signal point; and a logical sum between outputs of the first to fourth discriminating circuits. An OR circuit for performing processing and outputting an effective area determination signal; and an effective area determination signal detection circuit.
JP62274938A 1987-10-30 1987-10-30 Effective area judgment signal detection circuit Expired - Fee Related JP2587432B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP62274938A JP2587432B2 (en) 1987-10-30 1987-10-30 Effective area judgment signal detection circuit
CA000581582A CA1273069A (en) 1987-10-30 1988-10-28 Validity decision circuit capable of correctly deciding validity of an error signal in a multilevel quadrature amplitude demodulator
US07/264,150 US4859956A (en) 1987-10-30 1988-10-28 Validity decision circuit capable of correctly deciding validity of an error signal in a multilevel quadrature amplitude demodulator
AU24548/88A AU601665B2 (en) 1987-10-30 1988-10-31 Validity decision circuit capable of correctly deciding validity of an error signal in a multilevel quadrature amplitude demodulator
DE88118159T DE3882484T2 (en) 1987-10-30 1988-10-31 Validation decision circuit with the ability to decide on the validity of an error signal in a multi-level QAM demodulator.
EP88118159A EP0314196B1 (en) 1987-10-30 1988-10-31 Validity decision circuit capable of correctly deciding validity of an error signal in a multilevel quadrature amplitude demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62274938A JP2587432B2 (en) 1987-10-30 1987-10-30 Effective area judgment signal detection circuit

Publications (2)

Publication Number Publication Date
JPH01117450A JPH01117450A (en) 1989-05-10
JP2587432B2 true JP2587432B2 (en) 1997-03-05

Family

ID=17548638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62274938A Expired - Fee Related JP2587432B2 (en) 1987-10-30 1987-10-30 Effective area judgment signal detection circuit

Country Status (1)

Country Link
JP (1) JP2587432B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04298142A (en) * 1991-03-26 1992-10-21 Nec Corp Clock synchronization circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010818A (en) * 1983-06-29 1985-01-21 Fujitsu Ltd Automatic equalizing system
JPS6177452A (en) * 1984-09-25 1986-04-21 Nec Corp Method and device for multi-value orthogonal amplitude modulation
JP2534650B2 (en) * 1985-08-15 1996-09-18 日本電気株式会社 Demodulator
JPH0740679B2 (en) * 1985-08-15 1995-05-01 日本電気株式会社 Digital demodulation system

Also Published As

Publication number Publication date
JPH01117450A (en) 1989-05-10

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