JP2701280B2 - Effective area judgment signal generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an effective area determination signal generation circuit, and in particular, to a high multi-level quadrature amplitude modulation system in which a signal point arrangement on a phase plane is stepped. The present invention relates to an effective area determination signal generation circuit used in a demodulation device in a digital wireless communication system adopting the above. (Prior Art) As is well known, in digital wireless communication, a high-valued quadrature amplitude modulation (QAM) method is adopted from the viewpoint of effective frequency utilization. This includes various types such as the 64QAM system and the 256QAM system. However, in this QAM system, as shown in FIG. 7, for example, the arrangement of signal points on a phase plane is a square, so that the peak power-to-average power ratio of a modulated wave increases as the number of values increases, and the transmission power increases. It becomes susceptible to non-linear distortion of an amplifier or the like. Therefore, for example, as shown in FIG. 8, a quadrature amplitude modulation scheme (STEPPED-SQUARE) in which the signal point arrangement on the phase plane is stepped, thereby reducing peak power.
QAM system: hereinafter, simply referred to as “SS-QAM” system) (Japanese Patent Laid-Open No. 61-77452). Fig. 8 shows 256SS-
The signal point arrangement of the QAM method is shown. The outer shape connecting the outermost signal points is a regular octagon, and the signal points near the vertices of each square of the normal QAM method are deleted. By the way, in order to correctly demodulate a 256SS-QAM modulated wave, an automatic amplitude control signal (AGC), a carrier reproduction signal (APC),
In order to generate a DC offset control signal and a tap control signal of a transversal equalizer for equalizing fading distortion and the like in a propagation path, an error signal representing a deviation of a signal point from an ideal value is required. If the entire demodulation system including the transversal type equalizer is not correctly brought into a synchronous state, a correct error signal cannot be obtained. That is, the error signal is ninth.
As shown in the figure, the upward shift from the ideal value of each signal point is expressed as “1”, and the downward shift is expressed as “0”. The signal that should be received at signal point position B is signal point position A. Signal point position X which is closer to the signal point position A beyond the center threshold value of the same B.
, The error signal becomes "0", which indicates that the signal to be received at the signal point position A has been received with a downward shift, and is an erroneous error signal.
If controlled by a control signal generated based on this erroneous error signal, the entire demodulation system including the transversal equalizer diverges. , And during the reset period, the generation circuit of each control signal stops its operation. (Problems to be Solved by the Invention) As described above, in the conventional SS-QAM demodulation apparatus, since the control by the correct control signal cannot be performed while the entire demodulation system is not correctly drawn, each control signal is transmitted. An operation of resetting to the initial value is required, and during this reset period, the transversal equalizer stops its equalizing operation. Then, once out-of-synchronization occurs due to fading, etc., the demodulation system is not pulled in until the fading distortion is sufficiently reduced, and during this time, the transversal system equalizer cannot exhibit the inherent equalizing capability. There is. The present invention has been made in view of such problems,
The purpose is, in the demodulation device in SS-QAM system,
An object of the present invention is to provide an effective area determination signal generation circuit for obtaining a correct error signal that enables a correct control signal to be generated even when a demodulation system loses synchronization. (Means for Solving the Problems) In order to solve the problems, the effective area determination signal generation circuit of the present invention has the following configuration. That is, the effective area determination signal generation circuit according to the present invention provides an effective area determination signal used in a demodulation apparatus in a digital wireless communication system employing a high multi-level quadrature amplitude modulation method so that signal point arrangement on a phase plane is stepped. A signal generating circuit for performing a digitizing process on each of P-channel and Q-channel baseband signals acquired by the demodulation device, which are orthogonal to each other; A / D converter; and associating address information expressed in a logical state at sample point positions of output digital signals of the first and second A / D converters with signal point positions in the step-like signal point arrangement. Receiving means for receiving the digital signals output from the first and second A / D converters, Detecting the logical state at the sampling point position of the signal and referring to the table, the logical state is located in the area outside the outermost signal point position in the step-like signal point arrangement on the phase plane. The data signal and the error signal represented by the output digital signals of the first and second A / D converters assuming that this is due to the signal originally to be received at the position of the outermost signal point are correct. And an effective area determination circuit for outputting an effective area determination signal to be considered. (Operation) Next, the operation of the effective area determination signal generation circuit of the present invention configured as described above will be described. In the signal point arrangement on the phase plane, the error signal obtained in the arrangement area includes an error as shown in FIG.
The present invention focuses on the fact that an error signal obtained outside the arrangement area, that is, outside the position of the outermost signal point is an error signal for a signal to be received at the position of the outermost signal point. Only the area outside the position of the outer signal point is determined as the effective area. As described above, according to the effective area determination signal generating circuit of the present invention, each of the baseband signals of the P channel and the Q channel which are orthogonal to each other and acquired by the demodulator is digitized, and When the logical state at the sample point position of the signal is outside the position of the outermost signal point in the step-like signal point arrangement on the phase plane, the effective area judgment signal is output, so that the demodulation system loses synchronization. However, since a correct error signal can be obtained, that is, a correct control signal can be generated, the control system of the transversal equalizer can be quickly converged. This eliminates the need for a reset operation as in the prior art, so that the transversal equalizer has the effect of exhibiting its equalizing capability without stopping. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an effective area determination signal generation circuit according to one embodiment of the present invention. In FIG. 1, reference numerals 11 and 12 denote A / D converters and 13
Is an effective area determination circuit. P that are orthogonal to each other and obtained by a demodulation device (not shown)
The multi-level baseband signals of the channel and the Q channel are input to A / D converters 11 and 12 via input terminals 1 and 2, respectively. The clock signal applied to the input terminal 3 is supplied to the A / D converters 11, 12, and the effective area determination circuit 13 as an operation clock for determining the identification timing and the like. Here, each of the P-channel and Q-channel multi-valued baseband signals corresponds to the 256SS-QAM scheme (8th
), It is an 18-value signal. The A / D converters 11 and 12 convert the input signal (18-value baseband signal) into a 7-bit binary digital signal (5-bit data signal (D _{1 to} D ₅ )) according to the conversion rule shown in FIG. And a 2-bit error signal (composed of E ₁ and E ₂ ), and outputs the respective output signals to the effective area determination circuit 13. Since the A / D converter 11 is for the P channel, its output signal is a 5-bit data signal D _1p , D _2p , D _2p ,
D _3p , D _4p , D _5p and 2-bit error signals E _1p , E _2p . Similarly, since the A / D converter 12 is for the Q channel, its output signal is a 5-bit data signal.
D _1q , D _2q , D _3q , D _4q , D _5q and 2-bit error signals E _1q , E _2q . Note that the error signals E _1q and E _1p are
It is the same as that shown in the figure. The effective area determination circuit 13 receives each output digital signal of the A / D converter 11 and 12 and detects the logical state of the output digital signal at the sample point position.
In the signal point arrangement shown in the figure, the output signal S is set to “1” when indicating the outside of the position of the outermost signal point, and otherwise set to “0”.
It is output to the output terminal 4. That is, as shown in FIG. 9, when the received signal is within the signal point arrangement area on the phase plane, the error signal (E _1p , E _1
1q ) contains errors. However, in FIG. 3, the signal point position C indicates the outermost signal point position.
If the signal is received at a position Y outside the signal point, there is no signal point position above the signal point position C, so that the signal received at the position Y is received at the signal point position C closest to this. It can be said that the probability that the power signal is received with a shift is extremely high. That is, the error signal (E _1p or E _1q ) of the received signal at the position Y is “1”, which can be said to be giving a correct error signal. Therefore, in the present invention, the outside of the signal point arrangement area is defined as an effective area and the inside is defined as an invalid area, as indicated by hatching in FIG. 4, and only the error signals (E _1p , E _1q ) of the received signal entering the effective area are determined. Use it. As a result, a correct control signal can be generated. Next, the valid area determination circuit 13 reads the ROM (Read Only Memory).
y). That is, the ROM uses, as address information, the logical state of each of the output digital signals of the A / D converters 11 and 12 at the sample point position, and this ROM stores a table associating the address information with the signal point arrangement. Is set in advance. Table 1 shows an example of a table set in the ROM, and the setting procedure of this table will be described below. Considering the first quadrant as shown in FIG. 5 from the symmetry of each of the four quadrants in FIG. 4, the shaded area (effective area) in FIG. 5 is as shown in FIGS. 6 (a) to 6 (f). It can be decomposed into the six areas shown. 6A, the signal level on the Q-axis is 9 or more, which is the error signal E ₂ (in FIG. 2, E _2q ) Is “1”. FIG. 6 (b) shows the results on the P axis. The signal level is 9 or more, which is the case when the error signal E _2p is “1” in FIG. FIG. 6 (c) shows that the signal level on the P-axis is 5 or more (D _2p
= 1 and D _3p = 1, and D _2p = 1, D _3p = 0 and D _4p = 1, and D
_2p = 1, _D3p = 0, _D4p = 0 and _E1p = 1), and the signal level on the Q axis is 8 or more ( _D2q , _D3q , _D4q , and _E1q are all "1"). . This means that, for example, when expressing a region where the value on the P-axis is 5 or more, the value is 6. based on the bit assignment in FIG.
5 or more regions indicated by D _2p = 1 and D _3p = 1, and values between 5.5 and 6.
The region indicated by D _2p = 1, D _3p = 0 and D _4p = 1 of 5 has a value of 5
This is expressed in three areas, that is, the area indicated by D _2p = 1, D _3p = 0, D _4p = 0 and E _1p = 1 in 5.5. Similarly,
FIG. 6 (f) shows that the signal level on the P-axis has a value of 8 or more (D _2p , D
_3p, D _4p, E _1p are "1"), the signal level on the Q-axis value of 5 or more (D _2q = 1 and D _3q = 1, and _{D 2q = 1, D 3q =} 0 and D _4q =
1, and D _2q = 1, D _3q = 0, D _4q = 0 and E _1q = 1). Table 1 is set in this way, and in the table, the mark “x” indicates that either “0” or “1” may be used. Thus, D _{1p to} D _5p , E _1p , E _2p , D _{1q to} D _5q , E _1q , E _2q
When the bit pattern of the bit digital signal indicates the region shown in FIGS. 6A to 6F, the output signal S is "1".
Thus, an effective area determination signal can be generated. Then, only the data signal and error signal obtained when S = 1 are used as probable signals for each control, and the others are discarded. (Effects of the Invention) As described above, according to the effective area determination signal generation circuit of the present invention, each of the baseband signals of the P channel and the Q channel which are orthogonal to each other and acquired by the demodulation device is digitized. Performs processing and outputs an effective area determination signal when the logical state at the sample point position of each digital signal indicates that the digital state also exists outside the outermost signal point position in the step-like signal point arrangement on the phase plane. As described above, since the data signal and the error signal represented by the digital signal can be determined and used as being correct, it is possible to obtain a correct error signal even when the demodulation system is out of synchronization. Since a signal can be generated, a control system such as a transversal type equalizer can be quickly converged. This eliminates the need for a reset operation as in the related art, so that the transversal equalizer can exert its equalizing ability without stopping.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an effective area determination signal generation circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing a relationship between an input signal and an output signal of an A / D converter, and FIG. FIG. 3 is a view for explaining the principle of effective area determination, FIG. 4 is a view showing an effective area in the 256SS-QAM system, FIG. 5 is a view showing an effective area in the first quadrant in FIG. 4, and FIG. FIG. 7 is an exploded view of the region, and FIG.
FIG. 8 is a signal point arrangement diagram of the 6QAM system, FIG. 8 is a signal point arrangement diagram of the 256SS-QAM system, and FIG. 9 is an explanatory diagram of a conventional error signal determination system. 11, 12 A / D converter, 13 Effective area determination circuit.

Claims (1)

(57) [Claims] An effective area determination signal generation circuit used in a demodulation device in a digital wireless communication system employing a high multi-level quadrature amplitude modulation method in which a signal point arrangement on a phase plane is stepped; The generating circuit performs first and second digitizing processes on each of the baseband signals of the P-channel and the Q-channel which are orthogonal to each other and acquired by the demodulator.
A / D converter; and associating address information expressed in a logical state at sample point positions of output digital signals of the first and second A / D converters with signal point positions in the step-like signal point arrangement. Receiving the digital signals output from the first and second A / D converters, detecting the logical state of the output digital signals at sample point positions, and While the logical state exists in a region outside the outermost signal point position in the step-like signal point arrangement on the phase plane while referring to the above, this is originally received at the outermost signal point position. Said first and second A /
An effective area determination circuit that outputs an effective area determination signal that regards a data signal and an error signal represented by an output digital signal of the D converter as being correct. .