JP3987268B2 - Receiver and quadrature amplitude demodulation circuit thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides 2ⁿThe present invention relates to an improvement in a digital microwave receiver employing a (n = 2, 3,...) Value quadrature amplitude modulation method and a quadrature amplitude demodulation circuit thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, various communication systems have been developed with increasing communication needs and communication technology, and among them, there are digital microwave radio communication systems. This type of system, for example, wirelessly transmits digital data by modulating a carrier wave in the microwave band by a multi-level quadrature amplitude modulation (multi-level QAM: Quadrature Amplitude Modulation) system. Compared with the system, it is cheap and enables high-quality data transmission.
[0003]
In digital microwave radio communication systems employing quadrature amplitude modulation, 2ⁿA modulation / demodulation system for (n = 2, 3,...) Value QAM signals is used, and among these, 16QAM, 64QAM, 256QAM systems, etc., in which the number of I channel and Q channel signals are equal, are common. In addition to this, there is a 128QAM system in which the number of I channel and Q channel signals is different.
[0004]
By the way, in a wireless communication system employing this method, it is important to maintain the orthogonality between the I channel and the Q channel with high accuracy in the reception demodulator in order to prevent bit errors during reception demodulation.
[0005]
However, this type of conventional wireless communication system has not yet been known to have a mechanism that actively compensates for the orthogonality of both channels. In particular, as 128QAM, 256QAM, etc., the greater the number of signal points, the lower the tolerance to orthogonality deviation in principle, and there is a possibility that bit errors may occur due to slight deviation and communication quality may be degraded. .
[0006]
[Problems to be solved by the invention]
As described above, in the digital microwave radio communication system using the multi-level QAM system, as the number of signal points increases, the tolerance to the orthogonality shift between channels decreases, and bit errors and communication quality decrease. There was a problem that there was a high risk of occurrence.
[0007]
The present invention has been made in view of the above circumstances, and an object thereof is to maintain the orthogonality between channels with high accuracy regardless of the number of signal points, and to thereby improve the communication quality and the orthogonality thereof. An object of the present invention is to provide an amplitude demodulation circuit.
[0008]
Another object of the present invention is to make it possible to configure an offset control circuit of an analog / digital conversion circuit by a simple circuit such as an ASIC (Application Specific IC), an FPGA (Field Programmable Gate Array), etc. It is an object of the present invention to provide a receiver and a quadrature amplitude demodulating circuit thereof that are miniaturized and stable in operation.
[0009]
[Means for Solving the Problems]
  To achieve the above objectiveThe quadrature amplitude demodulation circuit according to the present invention has 2 ⁿ In an orthogonal amplitude demodulation circuit that demodulates an n-sequence digital signal from a received signal modulated by a value quadrature amplitude modulation method (n is a natural number of 2 or more), an I channel and a Q channel that are orthogonally demodulated by orthogonally demodulating the received signal A quadrature demodulator that outputs a demodulated signal, a digital converter that digitally converts the demodulated signal for each channel to obtain digital data for each of the I channel and Q channel, and a digital data for each of the I channel and Q channel. A signal point arrangement conversion unit for demapping the signal point arrangement on the two-dimensional phase plane to reproduce and output the n-sequence digital signal, and the two-dimensional phase plane based on the digital data for each of the I channel and Q channel An orthogonality compensation unit that compensates for the orthogonality between the I axis and the Q axis. A logic operation that generates a control signal for compensating the orthogonality by a logic operation that selectively uses digital data corresponding to a signal point that appears at least inside the outermost circumference on the two-dimensional phase plane. Characterized by comprising a part.
[0010]
In addition, the orthogonal signal regeneration unit includes, for example, a branch unit that branches the received signal, and a variable delay unit that delays the phase of one of the received signals branched by the branch unit,
By causing the orthogonality compensation means to control a phase delay amount in the variable delay means based on a logical operation result using a main signal and an error signal of digital data output from the digital conversion means, the orthogonal signal reproduction is performed. The quadrature relationship between the in-phase component and the quadrature component output from the means is compensated.
[0011]
By taking such means, it is possible to maintain the orthogonality between the I channel and the Q channel with high accuracy, and as a result, it is possible to suppress bit errors and improve communication quality.
[0012]
Particularly in the present invention, the orthogonality compensation means selectively uses only signal points appearing at least inside the outermost circumference on the two-dimensional phase plane, among the digital data output from the digital conversion means. The control for compensating the quadrature relationship between the in-phase component and the quadrature component output from the quadrature signal reproducing means is performed.
[0013]
That is, the signal point appearing in the region near the origin on the two-dimensional phase plane is more resistant to deviation than the signal point appearing outside. In other words, the range until the allowable deviation value (threshold value) is exceeded is wide. Taking advantage of this, the present invention limits the signal points used for orthogonality control to the inner signal points on the two-dimensional phase plane, thereby improving the accuracy of orthogonality control and stabilizing the control. Is possible. This is particularly effective when a multi-level QAM system having a large number of signal points, such as 128 QAM or 256 QAM, is employed.
[0014]
Further, by using signal points that are highly resistant to deviations in principle, it is possible to relax the demands on the characteristics of the elements that make up the circuit, thereby making it possible to reduce the cost of the device. .
[0015]
The receiving apparatus and the quadrature amplitude demodulating circuit according to the second aspect of the present invention receive the received signal as 2ⁿIn a quadrature amplitude demodulation circuit that demodulates an n-sequence digital signal according to a value quadrature amplitude modulation method (n is a natural number of 2 or more), or a reception device that uses this quadrature amplitude demodulation circuit,
The quadrature signal reproducing means for separating the in-phase component of the carrier wave from the received signal and the quadrature component orthogonal thereto and outputting these components separately; and the in-phase component and the quadrature component output from the quadrature signal reproducing means Digital conversion means for converting into digital data, digital signal reproduction means for reproducing the n-sequence digital signal from digital data output from the digital conversion means, and error signal of digital data output from the digital conversion means Are provided between the digital conversion means and the digital signal reproduction means, and the in-phase component output from the digital conversion means and The above-mentioned up / down is added to the digital data for each orthogonal component. The output from the counter is to and a digital adder for adding each.
[0016]
In this way, the error signal of the digital data output from the digital conversion means is counted by the up / down counter, and the counted value is added to the digital data, thereby correcting the error component of the identification level in the digital conversion means. Is done. Here, the up / down counter functions as an integrator.
[0017]
Conventionally, such an operation has been carried out by an analog element, but the same operation can be performed digitally by adopting the above configuration. In other words, the circuit for correcting the error component of the identification level in the A / D converter as the digital conversion means can be configured as an all-digital configuration. Therefore, the element can be configured inside an ASIC, FPGA, or the like, and the number of parts can be reduced. In addition, in the analog configuration, the constants may need to be finely adjusted due to element variations. However, since an all-digital configuration is possible, a stable operation can always be obtained.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiment, 128QAM (2⁷A quadrature amplitude demodulation unit of a digital transmission apparatus using the (value QAM) method will be described as an example.
[0019]
(First embodiment)
FIG. 1 is a circuit block diagram showing a configuration of a quadrature amplitude demodulator according to the first embodiment of the present invention. In FIG. 1, a reception intermediate frequency signal output from a reception circuit (not shown) is subjected to level adjustment by an automatic gain control amplifier 21 and then to a quadrature demodulation circuit 24 via a roll-off filter (ROF) 22 and a reception intermediate frequency amplifier 23. Entered.
[0020]
The quadrature demodulation circuit 24 separates the in-phase component of the carrier wave from the received signal and the quadrature component orthogonal thereto, and outputs these components separately. That is, the quadrature demodulation circuit 24 divides the received reception intermediate frequency signal into two and mixes it with the reference carrier wave generated by the voltage controlled oscillator (VCO) 241 respectively, so that the I channel and Q channel baseband demodulated signals are obtained. Output. At that time, the phase of the reference carrier wave given to the two-branch received intermediate frequency signal is made orthogonal to each other by the variable delay element 242 to obtain I channel and Q channel signal outputs orthogonal to each other. The phase delay amount in the variable delay element 242 is controlled by a control circuit (CONT) 38.
[0021]
Here, the frequency of the reference carrier wave generated by the VCO 241 is synchronized with the reception carrier frequency by a carrier wave synchronization circuit comprising a control circuit (CONT) 38 and a low-pass filter 331.
[0022]
The I-channel and Q-channel demodulated signals output from the quadrature demodulation circuit 24 are input to analog / digital (A / D) converters 29 and 30 via low-pass filters 25 and 26 and operational amplifiers 27 and 28, respectively. Converted to digital data. The received digital data I0 to I7 and Q0 to Q7 are input to the signal point arrangement conversion circuit 36. Further, the received digital data I0 to I7 and Q0 to Q7 are branched and input to the control circuit (CONT) 38 via the orthogonality compensation circuit 37.
[0023]
The signal point arrangement conversion circuit 36 includes a differential logic circuit (DIFFLOG) 341 and a demapping circuit 361. The difference logic circuit 341 performs a difference operation on the input received digital data I0 to I7 and Q0 to Q7. The demapping circuit 361 performs conversion processing for returning the signal point arrangement on the two-dimensional phase plane of the received digital data I0 to I7 and Q0 to Q7 output from the difference logic circuit 341 to the state before mapping. The data after demapping is reproduced and output as 8-series digital signals D1 to D8.
[0024]
In addition, reference numeral 31 in the figure denotes a clock recovery circuit (CLK REC). Reference numeral 40 denotes an interface unit (I / F), and reference numeral 50 denotes an operation unit. The user's input operation given by the operation unit 50 is notified to the control circuit 38 via the interface unit 40 to select a modulation method and It is reflected in the selection of the demapping method according to. Reference numerals 331 to 334 are all low-pass filters that average the control signals from the control circuit 38.
[0025]
FIG. 2 is a circuit diagram showing a configuration of the orthogonality compensation circuit 37 in the present embodiment. The orthogonality compensation circuit 37 includes EXNOR (negative exclusive OR) gates 2a and 2b, AND (logical product) gates 2c and 2d, and an OR (logical sum) gate 2e. Of these, the EXNOR gate 2a has an I channel MSB (Most Significant Bit) I7 and an error signal Q2 in the Q channel 128QAM, and the EXNOR gate 2b similarly has an Q channel MSB Q7 and an I channel error signal I2. Is given. The outputs of the EXNOR gates 2a and 2b are input to the AND gates 2c and 2d together with a clock signal that is inverted with each other (by a NOT element: unsigned), and the logical sum output (by the OR gate 2e) as a control signal NQUAD Is output.
[0026]
FIG. 2 shows a circuit configuration when an existing method called DRE1 / 2 (Decision Range Expanded 1/2) is applied in order to increase fading resistance. When DRE1 / 2 is not applied, the error signal is lowered by one step to become the fifth path (I3, Q3).
[0027]
Next, the operation in the above configuration will be described. First, an outline will be described with reference to FIG. This diagram is for explaining the concept of orthogonality compensation in the four-value QAM modulation system. In the two-dimensional phase plane, when the Q axis is shifted clockwise as shown in the figure, the signal point is detected in a shaded area as indicated by a white circle. The same applies when the I-axis is shifted counterclockwise. Therefore, by performing feedback control of the delay amount of the variable delay element 242 in FIG. 1 so as to eliminate the bias of the detection probability of the signal point in the shaded area, it is possible to maintain the orthogonality of the Q axis and the I axis with high accuracy. Become. In the present embodiment, a control signal for controlling the amount of delay applied to the variable delay element 242 is generated by a logical operation by the hardware logic circuit shown in FIG.
[0028]
Next, the concept of orthogonality compensation in the 16-value QAM modulation scheme to which DRE1 / 2 is applied will be described with reference to FIG. This figure shows a region for detecting a deviation between the Q-axis and the I-axis in the above method. As can be seen from the figure, in order to detect the shift between the Q axis and the I axis, it is preferable to employ a main signal after digital conversion and an error signal corresponding to the modulation method. Specifically, the exclusive OR of the Q-channel main signal and the I-channel error signal is used to detect the Q-axis deviation, and the I-channel main signal and the Q-channel are used to detect the I-axis deviation. It is only necessary to obtain an exclusive OR with the error signal.
[0029]
Therefore, in the 128 (256) QAM system under DRE1 / 2, the main signals are Q7 and I7 and the error signals are Q2 and I2. Therefore, in FIG. 2, the EXNOR gate 2a has I7 and Q2 and the EXNOR gate. Q7 and I2 are input to 2b. The outputs of these EXNOR gates 2a and 2b are supplied to AND gates 2c and 2d, respectively, ANDed with clocks that are inverted from each other, and further subjected to a logical sum operation (by OR gate 2e), thereby providing a variable delay. A control signal to be applied to the element 242 can be obtained.
[0030]
As described above, in this embodiment, a control signal for detecting a shift between the Q axis and the I axis by a logical operation using the main signal after digital conversion and an error signal corresponding to the modulation method, and correcting this. Is generated and applied to the variable delay element 242 and the amount of delay is controlled to maintain the orthogonality between the Q axis and the I axis with high accuracy. In the 128QAM modulation system shown in the present embodiment, the exclusive OR of the I channel MSB and the Q channel Q2 is inverted, and the exclusive OR of the Q channel MSB and the I channel I2 is inverted. These are logically ANDed with clock signals inverted from each other to obtain the logical sum of the two, and the result is used as a control signal.
[0031]
With such a configuration, the orthogonality between the I channel and the Q channel can be maintained with high accuracy, and the communication quality can be improved.
[0032]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of the orthogonality compensation circuit 37 in the second embodiment. This circuit includes EXOR (exclusive OR) gates 5a to 5d, edge triggered flip-flop circuits 38c and 38d, and AND (logical product) gates 5e and 5f.
[0033]
As shown in the figure, I7 and Q1 are input to the EXOR gate 5a, IQ1 and Q2 are input to the EXOR gate 5b, I1 and Q7 are input to the EXOR gate 5c, and I1 and I2 are input to the EXOR gate 5d, respectively. Of these, the outputs of the EXOR gates 5a and 5c are applied to the D terminals of the flip-flop circuits 38c and 38d, respectively.
[0034]
Outputs of the flip-flop circuits 38c and 38d are respectively supplied to AND gates 5e and 5f, and are logically ANDed with clock signals that are inverted from each other. The logical sum of the results is output as a control signal to the variable delay element 242 (by the OR circuit 2e).
[0035]
On the other hand, the AND of the output of the EXOR gate 5b and the clock signal is input to the clock terminal of the flip-flop circuit 38c. Similarly, the AND of the output of the EXOR gate 5d and the clock signal is input to the clock terminal of the flip-flop circuit 38d.
[0036]
The operation of the above configuration will be described with reference to FIG. FIG. 6 is a conceptual diagram for explaining another example of orthogonality compensation in a 16-value QAM modulation scheme to which DRE1 / 2 is applied. In this figure, the second bit of the error signal is used for the Q signal and the main signal MSB is used for the I signal in order to detect the deviation of the Q axis and the I axis.
[0037]
In FIG. 6, since the detection position of the signal point moves up and down when the I-axis is displaced, the detection region is detected by sandwiching black circles vertically for detecting the displacement of the I-axis, based on the same concept as in FIG. Should be set. On the other hand, when the Q axis is deviated, the signal point detection position moves greatly in the left-right direction, but slightly moves in the up-down direction (the same can be said for the I-axis). For this reason, the detection region may be set so that the black circles are sandwiched vertically between the Q-axis deviations. In this embodiment, in order to detect this slight deviation, the second bit of the error signal is used for the Q signal.
[0038]
In FIG. 6, 1 is output when a signal point appears in a region where a Q-axis shift is detected, 0 is output when a signal point appears in a region where a shift in the I-axis is detected, and other regions are displayed. When a logic circuit is formed as a dead zone (an area for holding the immediately preceding output), the result is as shown in FIG. Even with such a configuration, it is possible to obtain the same effects as those of the first embodiment.
[0039]
(Third embodiment)
Next, a form obtained by further improving the first and second embodiments will be described as a third embodiment. FIG. 7 is a diagram showing the relationship between signal point arrangement and orthogonality deviation in the 128QAM system.
[0040]
As is apparent from this figure, in the quadrature amplitude modulation method having a large number of signal points such as 128QAM, generally, the distance from the convergence point of each signal point due to the orthogonality deviation increases as the distance from the I axis and Q axis increases. Become. For example, if a signal point shift of 11.3 ° occurs in FIG. 7, the signal point (black point in the figure) and the convergence point (outline point in the figure) in the region 1 are in the same region. Although control can be performed, a signal error occurs in the region 2 because the signal point protrudes outside the region. That is, the point located in the outer region (region away from the origin) in the signal point arrangement diagram is less resistant to orthogonality deviation.
[0041]
However, in the first and second orthogonality compensation circuits 37, orthogonality control is performed using all the signal points that arrive at random. For this reason, there is a high possibility of erroneous control when a point located in a region away from the origin arrives, and orthogonality control tends to become unstable especially at the stage before the reception signal is drawn. In the present embodiment, an example in which this point is improved will be described.
[0042]
FIG. 8 is a circuit diagram showing a configuration of the orthogonality compensation circuit 37 according to the third embodiment. In the figure, parts common to those in FIGS. 2 and 5 are denoted by the same reference numerals, and only different parts will be described here.
[0043]
The circuit of FIG. 8 includes identification area detection circuits 38a and 38b. The identification area detection circuits 38a and 38b include an EXOR gate, an EXNOR gate, and an AND gate (not labeled). For example, in the identification region detection circuit 38a, I channel MSBs I7 and I6 are input to the EXOR gate, and I6 and I5 are input to the EXNOR gate, respectively. The logical product (by the AND gate) of the outputs of these gates and the clock signal is input to the clock terminal of the flip-flop circuit 38c. The output of the EXNOR gate 2a is given to the D terminal of the flip-flop circuit 38c. The identification region detection circuit 38b, the EXNOR gate 2b, and the flip-flop circuit 38d have the same configuration in which the Q channel and the I channel are interchanged.
[0044]
With reference to FIG. 9, the operation in the above configuration will be described. In the third embodiment, the position is limited to the point used for orthogonality control on the two-dimensional phase plane. That is, when orthogonality control is performed independently with respect to the Q axis and the I axis, signal points within a region surrounded by a solid line in the figure are surrounded by a dotted line in the figure for control in the I channel direction. Each signal point in the selected region is used, and the signal point detected outside this region is not used for orthogonality compensation control. In short, only 8 × 8 points located inside are selectively used for the orthogonality compensation control.
[0045]
This is shown in more detail as shown in FIG. This figure is a diagram showing an identification area in the present embodiment in a 256QAM system (which also applies to 128QAM) to which DRE1 / 2 is applied. From this figure, in order to distinguish the 8 × 8 points located in the center from the outside, the main signal and the lower 2nd bit (Q7, I7, Q6, I6, Q5, I5) for both channels are used. It turns out that it should be used. Specifically, for example, in the I channel, it is only necessary to distinguish the point where (I7, I6, I5) = (1, 0, 0) or (0, 1, 1) from the others (the Q channel is also completely different). The same).
[0046]
In the circuit of FIG. 8, the selective orthogonality control based on the appearance position of the signal point described above is realized as follows. For example, the I channel will be described. When (I7, I6, I5) = (1, 0, 0) or (0, 1, 1) due to the action of the EXOR gate and EXNOR gate of the identification region detection circuit 38a, (0, 0) is output to the AND gate of the stage. At this time, the clock signal supplied to the clock terminal of the flip-flop circuit 38c stops, and the output from the EXNOR gate 2a (that is, the orthogonality control signal to the variable delay element 242) is latched by the flip-flop circuit 38c. As for the state of orthogonality control, the previous state is maintained.
[0047]
As described above, in the present embodiment, a control for detecting a shift between the Q axis and the I axis by a logical operation using the main signal after digital conversion and an error signal corresponding to the modulation method, and correcting the shift. A signal is generated, and at that time, only 8 × 8 points located at the center of the signal point arrangement diagram are used to generate a control signal. Specifically, the lower 1 bit and 2 bits (Q6, I6, Q5, and I5) of the main signal are used, and when a point located outside the above range appears, the orthogonality control signal is latched. The previous signal is held.
[0048]
That is, the 128-value signal point constellation is composed of two orthogonal signals of 12 values each for Ich and Qch. In addition, orthogonality control is performed independently in the Ich direction and the Qch direction, but in this embodiment, when performing control in the Ich direction, each of the 12 values of Qch, each of the outer two values, for a total of four values, Do not use. Similarly, when controlling in the Qch direction, only the inner 8 values of the 12 values of Ich are used.
[0049]
As described above, when the orthogonality control is performed, the outer point having low resistance to deviation is not used, and only the inner point having high resistance is used, so that the orthogonality control of the I axis and the Q axis is highly accurate. As a result, communication quality can be improved. Further, the region on the signal point arrangement diagram used for orthogonality control can be arbitrarily set regardless of the number of signal points. This makes it possible to maintain the orthogonality between channels with high accuracy regardless of the number of signal points.
[0050]
Further, the orthogonality control method shown in the present embodiment is particularly effective in a situation where the orthogonality deviation is large, for example, immediately after the power is turned on. Taking advantage of this advantage, orthogonality control may be performed using all signal points after the initial control state is achieved and the control is stabilized to some extent. If such a method is used, the stability of the control can be further improved when the disturbance on the transmission medium is relatively small.
[0051]
Although FIG. 8 shows the configuration of the orthogonality compensation circuit when the DRE1 / 2 method is applied, the configuration when this method is not applied is as shown in FIG. In this configuration, the EXNOR gates in the identification area detection circuits 38a and 38b are deleted as compared with FIG.
[0052]
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 12 is a circuit block diagram showing the configuration of the quadrature amplitude demodulator in the fourth embodiment. In the figure, parts common to those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described here.
[0053]
In FIG. 12, the gains of the operational amplifiers 27 and 28 for performing the offset adjustment of the analog / digital (A / D) converters 29 and 30 are fixed, and instead of this, adders 101 and 102 and an up / down counter (U / D) COUNT) 103, 104.
[0054]
The up / down counter 103 receives I6 (I channel error signal) of the digital data output from the A / D converter 29, and the up / down counter 104 stores Q6 (Q channel from the A / D converter 30). Error signal). The 8-bit parallel output signals of the up / down counters 103 and 104 are supplied to adders 101 and 102, respectively, and added to the output data of the A / D converters 29 and 30 for each bit sequence to form a feedback loop. . Each of the up / down counters 103 and 104 is preferably composed of about 20 stages.
[0055]
In the above configuration, the control circuit (CONT) 38 detects the variation of the identification level in the A / D converters 29 and 30 (that is, the variation direction of the identification level corresponding to the error signal) from the eye pattern of the digital demodulated signal. The result is given to the up / down counters 103 and 104 and counted to perform averaging. That is, the up / down counters 103 and 104 perform the same operation as the integrator.
[0056]
As a result, the up / down counters 103 and 104 output a signal in which the variation of the identification level is inverted (a signal having the same level and the opposite sign), and this is added to the original signal by the adders 101 and 102. Thus, it is possible to obtain a digital output in which the fluctuation of the offset level of the A / D converters 29 and 30 is suppressed.
[0057]
In the configuration of FIG. 1, due to an increase in carrier leak in the modulation circuit (not shown) on the transmitter side, fluctuations in the DC offset level of the operational amplifiers 27 and 28, fluctuations in the reference voltages of the A / D converters 29 and 30, and the like. Variations in the identification level during A / D conversion are compensated by controlling the bias voltages of the operational amplifiers 27 and 28. That is, after the output from the control circuit (CONT) 38 is averaged by the low-pass filter (integrator) 333, the bias voltages of the operational amplifiers 27 and 28 are controlled. Therefore, the control is analog, and it is weak against external factors such as temperature fluctuations, and there is an inconvenience that it is necessary to adjust the operation constant due to variations in element characteristics.
[0058]
On the other hand, in this embodiment, the error signal of each channel is counted by the up / down counters 103 and 104, and the result is added to the original signal by the adders 101 and 102, thereby identifying at the time of A / D conversion. Compensation for level fluctuations can all be performed digitally. This makes it possible to eliminate the inconveniences described above and stabilize the operation.
[0059]
Further, according to the present embodiment, the quadrature amplitude demodulating circuit can be digitized entirely, which allows a simple digital element such as an ASIC, FPGA, or PLD (Programmable Logic Device) to be used. Benefits such as reduction can also be obtained.
[0060]
The present invention is not limited to the above embodiment. For example, in the above embodiment, a 128-value quadrature amplitude modulation method has been proposed. However, the idea of the present invention is that digital data after A / D conversion is used. It is also possible to apply to multi-value quadrature amplitude modulation schemes such as 64 values, 256 values, etc. by arbitrarily setting the acquisition region.
[0061]
In addition, the control effective / region distinction in the first embodiment is not limited to the 8 × 8 region described above, but is arbitrarily set according to the element characteristics and according to the amount of orthogonality deviation before pull-in. It is possible.
In addition, various modifications can be made without departing from the scope of the present invention.
[0062]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to stabilize compensation control of orthogonality between channels regardless of the number of signal points, and thereby a receiving apparatus and communication apparatus for improving communication quality and its orthogonal amplitude. A demodulation circuit can be provided.
Further, according to the present invention, the offset control circuit of the analog / digital conversion circuit can be configured by a simple circuit such as an ASIC, FPGA, etc., and thereby a receiving apparatus that achieves a reduction in circuit scale and stabilization of operation. And a quadrature amplitude demodulation circuit thereof.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a configuration of a quadrature amplitude demodulation circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of an orthogonality compensation circuit 37 in the first embodiment of the present invention.
FIG. 3 is a diagram for explaining the concept of orthogonality compensation in a four-value QAM modulation system.
FIG. 4 is a diagram for explaining a concept of orthogonality compensation in a 16-value QAM modulation scheme to which DRE1 / 2 is applied.
FIG. 5 is a circuit diagram showing a configuration of an orthogonality compensation circuit 37 in the second embodiment of the present invention.
FIG. 6 is a conceptual diagram for explaining another example of orthogonality compensation in a 16-value QAM modulation scheme to which DRE1 / 2 is applied.
FIG. 7 is a diagram showing the relationship between signal point arrangement and orthogonality deviation in 128QAM.
FIG. 8 is a circuit diagram showing a configuration of an orthogonality compensation circuit 37 in the third embodiment of the present invention.
9 is a diagram used for explaining the operation of the orthogonality compensation circuit 37 in FIG. 8;
FIG. 10 is a diagram showing an identification area in a 256QAM system (same for 128QAM) to which DRE1 / 2 is applied according to the third embodiment of the present invention.
FIG. 11 is a circuit diagram showing a configuration of an orthogonality compensation circuit 37 when the DRE1 / 2 method is not applied in the third embodiment of the present invention.
FIG. 12 is a circuit block diagram showing a configuration of a quadrature amplitude demodulation circuit according to a fourth embodiment of the present invention.
[Explanation of symbols]
21 ... Automatic gain control amplifier
22 Roll-off filter (ROF)
23. Reception intermediate frequency amplifier
24. Quadrature demodulation circuit
241 ... Voltage controlled oscillator (VCO)
242 ... Variable delay element
25, 26 ... low-pass filter
27, 28 ... operational amplifier
29, 30 ... Analog / digital (A / D) converter
31 ... Clock recovery circuit (CLK REC)
331-334 ... Low-pass filter
36. Signal point arrangement conversion circuit
341 ... Differential logic circuit (DIFFLOG)
361: Demapping circuit
37 ... Orthogonality compensation circuit
38 ... Control circuit (CONT)
2a, 2b ... EXNOR (Negative exclusive OR) gate
2c, 2d ... AND gate
2e ... OR (logical sum) gate
5a, 5b, 5c, 5d,... EXOR (exclusive OR) gate
5e, 5f ... AND (logical product) gate
38a, 38b ... identification area detection circuit
38c, 38d ... flip-flop circuit
40. Interface part (I / F)
50. Operation unit
101, 102 ... adder
103, 104 ... up / down counter (U / D COUNT)

Claims (2)

2 In a quadrature amplitude demodulation circuit that demodulates an n-sequence digital signal from a received signal modulated by an ^n- value quadrature amplitude modulation method (n is a natural number of 2 or more)
An orthogonal demodulator that orthogonally demodulates the received signal and outputs demodulated signals of I channel and Q channel orthogonal to each other ;
A digital converting unit that the demodulated signal to digital conversion for each channel to obtain a digital data for each of the I and Q channels,
A signal point arrangement conversion unit for demapping the signal point arrangement on the two-dimensional phase plane of the digital data for each of the I channel and the Q channel and reproducing and outputting the n-sequence digital signal ;
An orthogonality compensation unit that compensates for the orthogonality between the I axis and the Q axis in the two-dimensional phase plane based on the digital data for each of the I channel and the Q channel;
This orthogonality compensation unit
A logic operation unit that generates a control signal for compensating for the orthogonality by a logic operation that selectively uses digital data corresponding to a signal point that appears at least inside the outermost circumference on the two-dimensional phase plane; A quadrature amplitude demodulation circuit. 2 ⁿ In a receiving apparatus that demodulates an n-sequence digital signal by a quadrature amplitude demodulation circuit from a received signal modulated by a value quadrature amplitude modulation method (n is a natural number of 2 or more)
The quadrature amplitude demodulation circuit includes:
An orthogonal demodulator that orthogonally demodulates the received signal and outputs demodulated signals of I channel and Q channel orthogonal to each other;
A digital converter for digitally converting the demodulated signal for each channel to obtain digital data for each of the I channel and Q channel;
A signal point arrangement conversion unit for demapping the signal point arrangement on the two-dimensional phase plane of the digital data for each of the I channel and the Q channel and reproducing and outputting the n-sequence digital signal;
An orthogonality compensation unit that compensates for the orthogonality between the I axis and the Q axis in the two-dimensional phase plane based on the digital data for each of the I channel and the Q channel;
This orthogonality compensation unit
A logic operation unit that generates a control signal for compensating for the orthogonality by a logic operation that selectively uses digital data corresponding to a signal point that appears at least inside the outermost circumference on the two-dimensional phase plane; A receiving apparatus.

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