JPH03123146A - Digital modulating and demodulating system - Google Patents

Abstract

PURPOSE:To improve the code error rate characteristic of a sub-data signal by changing the modulation phase quantity caused by the sub-data signal in accordance with a modulation amplitude value of a main data signal. CONSTITUTION:Main data signals X1, 2 and Y1, 2 and a sub-data signal D are inputted to a ROM 15 and 16, and a multi-bit binary signal is generated. Outputs of a D/A converter 17 and 18 pass through a low-pass filter 19 and 20, respectively and inputted to an orthogonal modulator constituted of a multiplier 21 and 22 and a pi/2 phase shifter 23. In such a state, in the case an amplitude value of the main data signal is maximum and intermediate, the phase modulation quantity by the sub-data signal is set to 2alpha radians, and in the case the amplitude value of the main data signal is minimum, the phase modulation quantity by the sub-data signal is set to 2beta radians (beta>alpha), and an orthogonal modulation is performed to an intermediate frequency signal of a local oscillator 24. In such a way, the code error rate characteristic of the sub-data signal is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital modulation/demodulation system in which a main data line using quadrature amplitude modulation uses phase modulation to compositely transmit a sub data signal.

[Prior Art] Due to its high efficiency, quadrature amplitude modulation has recently become the mainstream of carrier wave digital transmission systems.

In order to efficiently transmit a sub data signal on a main data line using orthogonal amplitude modulation, a digital modulation/demodulation system has been proposed in which a quadrature amplitude modulated wave modulated by the main data signal is 2α radian phase modulated with the sub data signal. (Patent Application No. 61-24950).

Here, the above digital modulation and demodulation system will be explained.

FIG. 6(a) is a signal arrangement diagram of a composite modulated wave obtained by ±α radian phase modulation of a 16-value orthogonal amplitude modulated wave.

16 signal points C('+J
is an integer from 1 to 4) is the signal point A+1 or Bl with phase modulation of ±α radians by the sub data signal.

is converted to

If the signal point is A or B1. from a complex modulated wave.

The signal is reproduced into a main data signal and a sub data signal as described below.

First, quadrature phase detection is performed on a complex modulated wave to obtain a demodulated output P which is an orthogonal projection of signal point A1 or B1 onto the P and Q axes. ,Qo
get.

Demodulation output P. , Qo at the discrimination levels of ±L and ±3L and the data obtained by discriminating them at the discrimination level of 0. The sub data signal can be reproduced by logically operating the data obtained by discriminating the data at the discrimination level of 0. Furthermore, the demodulated output P is obtained by using the circuits shown in FIGS. 7 and 9 shown in Japanese Patent Publication No. 58-698 "Phase Synchronized Circuit". ,Q.

It is also possible to reproduce the sub data signal from.

Demodulation output P. , Qo is multivalued through a 10α radian phase shifter and a −α radian phase shifter, which are analog calculation circuits, and one of the obtained output data is selected in correspondence with the previously obtained sub data signal. By selecting, the main data signal can be reproduced.

Since the identification margin of the sub data signal is smaller than that of the main data signal, if the code transmission speeds of both data signals are the same, the code error rate characteristics of the sub data signal will deteriorate, and the main data signal will be affected by signal errors in the sub data signal. Since the reproduction of the data signal is also erroneous, the code transmission speed of the sub data signal is reduced to an integer (m)th of the code transmission speed of the main data signal, and the improvement effect is achieved by limiting the band.

Alternatively, it is necessary to sufficiently improve the bit error rate characteristics of the sub data signal through the improvement effect of majority decision or the like.

In addition, if you increase the value of α, the bit error rate characteristics of the sub data signal will improve, but on the other hand, the bit error rate characteristics of the main data signal will worsen, so there is a limit to its value, and in the case of 16 values , approximately 0.16 radian.

In this case, although it varies depending on the signal point, the C/N deterioration amount is about 6 dB with respect to the main data signal at the best point. In the case of 16 values, it is possible to reduce the value of 1 m to about 8.

[Problems to be solved by the invention] If the above-mentioned conventional digital modulation and demodulation system is used,
By appropriately selecting the values of α and m, the sub data signal can be transmitted without deteriorating the bit error rate of the main data signal.

However, in this system, the amount of phase modulation by the sub data signal is constant at α radians, regardless of the amplitude value of the modulated wave by the main data signal.

Therefore, the C/N value of the sub data signal reproduced on the demodulation side varies greatly depending on the modulation amplitude value of the main data signal.

Referring to FIG. 6(a), when the modulation amplitude value of the main data signal is maximum, the signal level of the sub data signal is obtained as AIIB, and when it is minimum, it is A14J4. In this way, there is a difference of about 9 dB between the two.

The bit error rate characteristic of the sub data signal is the worst value A14B14
, and it is not possible to increase the amount of information in the sub data signal. In other words, the conventional digital modulation/demodulation system is inefficient.

An object of the present invention is to change the amount of modulation phase by a sub data signal in accordance with the modulation amplitude value of a main data signal.

An object of the present invention is to provide a digital modulation/demodulation system that can further improve the bit error rate characteristics of a sub data signal.

[Means for Solving the Problems] In the digital modulation/demodulation system of the present invention, a modulation device converts orthogonal amplitude modulated waves modulated with a main data signal having a code transmission rate f1 into sub-waves having a code transmission rate f2 (f, > f2). When modulating with a data signal, the device includes means for selecting one value from at least two values, 2α radian and 2β radian, according to the amplitude value of the orthogonal amplitude modulated wave, and performing phase modulation to obtain a composite modulated wave; The apparatus includes means for performing quadrature phase detection on the composite modulated wave to obtain first and second demodulated signals, and calculating the data signal obtained by performing multi-value identification on the demodulated signal to reproduce the sub data signal. level determination means for receiving the data signal to determine the amplitude value of the composite modulated wave and outputting a determination signal; and main data signal reproducing means for controlling the phase of 2β radians and reproducing the main data signal.

[Example] The present invention will be explained in detail below using examples.

FIG. 1(a) is a block diagram showing an embodiment of the modulation device according to the present invention, and shows the case where the main data signal is 16QAM, and the modulation signal device shown in FIG. 6(b) is obtained. It is composed of

In FIG. 6(b), when the amplitude value of the main data signal is between the maximum and the middle (maximum: A14B14 middle; A 12 B 1
21AIBB131 (where i is 1 to 4), the amount of phase modulation by the sub data signal is 2α radian, and when the amplitude value of the main data signal is the minimum (minimum; A 14814)
−＼・ The phase modulation amount by the sub data signal is 2β radian (β
〉α). Here, the main data signal is 16QAM
In this case, the value of β can be set up to about twice the value of α.

Referring to FIG. 1(b), the main data signal (Xl).

2 and Yl, 2) and the sub data signal (D) are input to ROMs 15 and 16, where a multi-bit binary signal is created by orthogonally projecting the signal arrangement of FIG. 6(b) onto the P and Q axes. 1
Next, it is converted into an analog quantity by D/A converters 17 and 18. The outputs of the D/A converters 17 and 18 are input to a quadrature modulator including multipliers 21 and 22 and a π/2 phase shifter 23 via low-pass filters (LPF) 19 and 20, respectively. Here, the intermediate frequency (IF) signal of the local oscillator 24 is subjected to orthogonal modulation. As a result, the modulated signal arrangement shown in FIG. 6(b) is obtained as an output.

Here, referring to FIG. 1(a), a demodulation device used in the present invention includes an intermediate frequency amplifier 1 for amplifying an input signal IN.
, a voltage controlled oscillator (hereinafter referred to as VCO) 2, the amplified output of the intermediate frequency amplifier 1, and the oscillation output of VC02 are input, and a demodulated output P is obtained. A quadrature phase detector 3 that outputs +Qo, a baseband amplifier 4.5 that amplifies demodulated outputs Po and Qo, respectively, and inputs the amplified outputs of the baseband amplifiers 4.5 and outputs demodulated data D, , D, Analog-to-digital converter (hereinafter referred to as A-D converter) 6, 7
, the demodulated data D, and the sub data signal S.
a sub data signal reproducing circuit 8 that outputs demodulated data D,
and a delay circuit 13 that delays the output by the amount of delay of the sub data signal reproducing circuit 8; and a level determination circuit 14 that inputs the output of the delay circuit 13 and determines the amplitude value of the main data signal.
Delay circuit 14 output, discrimination signal H and sub data signal S
are input, and the main data signals Xi, X2 . Yl, Y2 and data signal X3. The main data signal reproducing circuit 9 outputs the data signal X3. A low pass filter (hereinafter referred to as LPF) inputs Y3 and outputs the signal to baseband amplifiers 4 and 5.
) 10 and data signals XI, X3 . Logic circuits 11 and 12 are provided to input Yl and Y3. The logic circuit 11 includes an intermediate frequency amplifier 1. A signal is output to baseband amplifier 5, and logic circuit 12 outputs a signal to VCO2.

This demodulator is an example in which 16-value orthogonal amplitude modulation is used as a modulation method for main data signals, and one-manpower signal IN is used as main data signals XI, X2, . 16 modulated by Yl and Y2
Value-orthogonal amplitude modulated wave (the normal position of its signal point is shown in Figure 6 (b)
) is a complex of intermediate frequency bands in which the sub data signal S is phase-modulated by ±α radians when the amplitude value of the 16-value orthogonal amplitude modulated wave is at the maximum, and ±β radians when the amplitude value is at the minimum. It is a modulated wave, and its signal point is A1 in Fig. 6(b).
1°Bl. Among the main data signals, signal points CI,
It is assumed that Xi and X2 determine the position in the P-axis direction, and Yl and Y2 determine the position in the 2Q-axis direction.

Also, the main data signal that determines the quadrant of the signal point is XI.

Suppose that it is Yl. Note that the code transmission rate of the sub data signal is set to 1/m of the code transmission rate of the main data signal.

The input signal IN is amplified to a predetermined amplitude by the intermediate frequency amplifier 1, and quadrature phase detected by the quadrature phase detector 3 using the output of the VCO 2 as a reference phase. Demodulation output P which is the detection output. +
Qo is the orthogonal projection of the signal point Aij or B onto the P and Q axes.

Demodulation output P. , Qo are amplified to a predetermined amplitude by respective baseband amplifiers 4.5, and A-D converters 6.7.
The demodulated data Dp is subjected to multivalue identification.

D. The greater the number of bits in the demodulated data D, ,D, the better the accuracy of subsequent signal processing, but in the case of 16 values, about 8 bits is sufficient.

The sub data signal reproducing circuit 8 will be described later.

It is configured with a logic circuit and a digital arithmetic circuit. The logic circuit outputs coefficient data corresponding to the demodulated data D,,D,. The digital arithmetic circuit performs digital arithmetic operations on the coefficient data and demodulated data Dp, D, and reproduces the sub data signal S.

The main data signal reproducing circuit 9 will also be described later.

It is equipped with a logic circuit and a digital arithmetic circuit.

1 2 The logic circuit outputs coefficient data in response to the sub data signal S output by the sub data signal reproducing circuit 8.

The digital arithmetic circuit removes the phase modulation component by the sub data signal S from the demodulated data Dp, D by digitally computing the coefficient data and the demodulated data Dp, D. The most significant bit and second bit of the two data obtained in this way are the main data signals XI, Y
l and X2°Y2. The third-order bit is the data signal X3, Y3.

Data signal X3. Since Y3 is a signal representing the deviation from the normal value of the input signals of the A/D converters 6 and 7, the output DC level of the baseband amplifier 4 is the output of the 2-digital signal X3 which is low-pass filtered by the LPFIO.

Furthermore, by controlling the output DC level of the baseband amplifier 5 with the output obtained by low-pass filtering the data signal Y3 with the LPFIO, it is possible to compensate for the drift of the DC component of the input signal of the A-D converter 6.7. .

The operation of this DC drift compensation is described in the "Demodulator" by the present inventor (Japanese Patent Application Laid-open No. 101449/1983).
is described in detail.

The logic circuit 11 receives data signals Xi, X3 . Yl and Y
This is a circuit that maintains the input signal amplitude of the A-D converter 6.7 at a normal value by controlling the gains of the intermediate frequency amplifier 1 and the baseband amplifier 5 with the two signals obtained from 3.
Its configuration and operation are described in detail in ``Automatic Gain Control Circuit'' (Japanese Unexamined Patent Publication No. 169256/1983) by the present inventor.

The logic circuit 12 receives data signals Xi, X3 . Yl and Y
This circuit forms a phase-locked loop by controlling VCO2 with the signal obtained from 3. Its configuration and operation are described in 1. "Carrier Regeneration Circuit" by the present inventor (Japanese Unexamined Patent Publication No. 57-1999).
131151)).

FIGS. 2(a) and 2(b) show the sub data signal reproducing circuit 8.
FIG. 2 is a block diagram showing two configuration examples.

The sub-data signal reproducing circuit 8 shown in FIG.
, and coefficient data M p 1 * M Q + are input, and the multiplier 83 receives the output of the multiplier 82 from the multiplier 82 .
and a subtracter 84 for subtracting the output of.

A majority decision circuit 85 is provided which inputs the output of the subtracter 84 and outputs a sub data signal S.

Logic circuit 81 receives main data signals Xi, X2 and Yl.
, Y2, and the upper two of the demodulated data D corresponding to Y2.
The position of the signal point C0 from the bit (i.

value of j), and the coefficient data M is determined in accordance with the result of 1 determination.
, and output M91.

This correspondence relationship is shown in FIGS. 3(a) and 3(b). Third
Figure (a) shows signal point C1 and coefficient data M,..., MQ+
FIG. Figure 3 (b
) is an explanatory diagram showing the correspondence between the signal point C1 and the polarity of coefficient data M, . . . MQ+.

When the signal point C1 is in the first quadrant or the third quadrant (i is 1 or 3. is converted into data corresponding to the vicinity of signal point A Hl, and signal point Bl,
Demodulated data D, corresponding to .

D, into data corresponding to the vicinity of signal point Bll.

As a result, the data string output by the subtractor 84 is:

It isometrically represents the analog quantity of the sub data signal S.

The most significant bit of these becomes data indicating that it is positive when the signal point is A1, and negative when the signal point is B1. If the signal point C0 is in the second or fourth quadrant (i is 2 or 4.j is 1 to 4), the multiplier 8
2.83 is the demodulated data Dp, DQ corresponding to the signal point AI or Bl, near the signal point B31 or the signal point A3I.
Since it is converted into data corresponding to the vicinity, in this case as well, the most significant bit of the data string output by the subtracter 84 becomes data indicating that the signal point is positive when it is A, and negative when it is B. . Therefore, by checking whether the most significant bit of the data string output by the subtracter 84 is positive or negative, it can be determined whether the signal point is A11 or Bl.In other words, the sub data signal S can be obtained. It will be done.

Since the data string output speed of the subtracter 84 is equal to the code transmission speed of the main data signal, the subtracter 84 outputs 1 of the sub data signal S.
A data string is output m times for the code. The majority decision circuit 85 counts the most significant bit of the output of the subtracter 84 m times, makes a majority decision, and outputs one decision result as a sub data signal S for a period of m times.

This majority logic operation improves the bit error rate characteristics of the sub data signal S.

The sub data signal reproducing circuit 8 shown in FIG. 2(b) is.

The majority decision circuit 85 is removed from the sub data signal reproducing circuit 8 shown in FIG.
．． It is configured by adding an A-D converter 88.

The data string output from the subtracter 84 is converted into an analog value by a DA converter 86, band-limited by an LPF 87, and digitized by a 1-bit AD converter 88 to become a sub data signal S. By limiting the band of the LPF 87, the bit error rate characteristics of the sub data signal S are improved. The band of the LPF 87 is set to around 1/m of the code transmission rate of the main data signal.

FIG. 4 is a block diagram showing the main data signal reproducing circuit 9. As shown in FIG.

The main data signal reproducing circuit 9 shown in FIG. 4 receives the sub data signal S, coefficient data M, 2 . A logic circuit 92 that outputs M, 2, a multiplier 93 that inputs demodulated data D and coefficient data Mp2, and a multiplier 94 that inputs demodulated data D and coefficient data MQ2.

Input the demodulated data D and the output data of the multiplier 93,
It includes an adder 95 that outputs data signals X1 to X3, and an adder 96 that receives demodulated data D and the output data of multiplier 94 and outputs data signals Y1 to Y3.

A delay circuit 13 provided at the input of the main data signal reproducing circuit 9 delays the demodulated data D, , D. This delay time is the first demodulated data D used to obtain one code of the sub data signal S.

D is set to the time from input to the sub data signal reproducing circuit 8 to the beginning of that code of the sub data signal S. With this setting, while one code of the sub data signal S is input to the main data signal reproducing circuit 9, the demodulated data D, , D used to obtain that code.

is input to multipliers 93.94 and adders 95.96.

The logic circuit 92 generates coefficient data M112+Mq having the relationship shown in FIG. 5 in response to the sub data signal S and the level determination signal H.
Outputs 2. In the figure, when the H signal is 1, the amplitude value of the main data signal is maximum or intermediate, and when the H signal is O, it is minimum.

Digital operations by multipliers 93.94 and adders 95.96 are performed using addition result data D of adders 95.96.
If expressed as 95+D 96, the case where the H signal is 1 can be written as follows.

However, when the value of the sub data signal S corresponds to the signal point AI (1 to 3 degrees), the upper positive and negative sign corresponds to the signal point B l (1 to 3 degrees).

When corresponding to , take the lower sign.

Equation (1) shows that if the coefficient (1/cos α) whose value is constant is ignored, signal points AI+1 to 3) or B1,1 to 3. The vector (Dp, D,) corresponding to α radians or one α
Since it is a formula that rotates in radians, the demodulated data Dp
, D, is the data corresponding to the signal point A I (1 to 3) or the data corresponding to the signal point B l (1 to 3), the data D 91. D , 6 is the signal point Cz+ ~,
.

The data corresponds to The same applies when the H signal is 0 (the main signal is the minimum), and the main data signal reproducing circuit 9 generates the vector (D, , DQ) corresponding to the signal point A14 or B10.
is rotated by β radians or -β radians, so whether demodulated data Dp, D, corresponds to signal points A, 4 or signal point B14, data D , , D , 6 is data corresponding to signal point CI4. therefore.

The data D 95+ D , 6 is data obtained by removing the phase modulation component by the sub data signal S from the demodulated data D, , D.

Adders 95 and 96 receive addition result data D9. ．． The upper 3 bits of D96 are used as data signals X1 to X3, Y1 to
Output as Y3.

As explained above, in the present invention, when the amplitude value of the main data signal 9 is the minimum, the modulation phase amount of the sub data signal is
β radians can be reduced by approximately 20
It is possible to improve the C/N ratio of log (sin β/sin α) and improve the bit error rate characteristics of the sub data signal. In other words, there is an advantage that the code speed ratio m between the main signal and the sub signal can be reduced.

Note that if the ratio of α and β is too large, the error ripple effect of the discrimination signal H will deteriorate the code error characteristics of the main signal.
In the case of M, an improvement of 3 to 5 dB can be expected. Further, in the embodiment, when the amplitude value of the main signal is the maximum or intermediate, the modulation phase amount of the sub data signal is the same as 2α radian, but it is also possible to optimize the two by dividing the two.

As described above, the modulation method of the main data signal is 16-value orthogonal oscillation
The present invention has been described in detail with respect to the case of modulation, but the present invention applies to modulation of 1 to 6 values or more, that is, 32 values.

64 value + ”; 25 b value, etc. can be similarly applied.

In that case, A,-1) increase the number of bits of the converters 6 and 7, increase the types of coefficient data of the logic circuit 91, and increase the amount of phase modulation (α, β, etc.) of the sub data signal and the value of m. All you have to do is change. Note that the sub data signal and the main data signal do not need to be synchronized in timing, and can operate even in an asynchronous state.

[Effects of the Invention] As explained above, in the digital modulation/demodulation system according to the present invention, the C/N value of the sub data signal can be reduced by about 20% compared to the conventional system.
By improving log (sin β/sin α), the information amount of the xl data signal can be increased.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing an embodiment of the demodulating device of the present invention, FIG. 1(b) is a block diagram showing an embodiment of the modulating device of the present invention, FIG. 2(a) and (b) is a block diagram showing a configuration example of the sub data signal reproducing circuit in the embodiment shown in FIG. 1, and FIGS. 3(a) and (b) are
FIG. 2 is an explanatory diagram showing the input/output relationship of the logic circuit in the sub data signal reproducing circuit shown in (a) or (b), and FIG. 4 is a block diagram showing the main data signal reproducing circuit in the embodiment shown in FIG. 1. 5 is an explanatory diagram showing the input/output relationship of the logic circuit in the main data signal reproducing circuit shown in FIG. 4. FIG. FIG. 6(a) is a signal arrangement diagram of a conventional complex modulated wave,
FIG. 6(b) is a signal arrangement diagram of a complex modulated wave according to the present invention. 1... Intermediate frequency amplifier, 2... VCo, 3... Quadrature phase detector, 4, 5... Baseband amplifier, 6.
7... A-D converter, 8... Sub data signal reproducing circuit, 9... Raw data signal reproducing circuit, 10... LPF,
, 11゜12...Logic circuit, 13...Delay circuit, 1
4... Level discrimination circuit, 15.16... ROM, 1
7.18...D/A converter, 19.20...LPF
, 21.22...multiplier, 23...π/2 phase shifter,
24...Local oscillator. 81...Logic circuit, 82.83...Multiplier, 84.
...Subtractor 192...Logic circuit, 93.94...Multiplier, 95.96...Adder. 3

Claims (1)

[Scope of Claims] 1. A first modulating means for modulating a carrier wave with a main data signal at a first code transmission rate to obtain an orthogonal amplitude modulated wave; When modulating with a sub data signal having a smaller second code transmission rate, one of a plurality of phase values is selected according to the amplitude value of the quadrature amplitude modulated wave, and the quadrature amplitude modulated wave is modulated at the selected phase value. and second modulation means for phase modulating the phase modulated wave to obtain a composite modulated wave. 2. It is used together with the transmitter according to claim 1, and performs orthogonal phase detection of the complex modulated wave to detect the first and second signals.
a first demodulating means for obtaining a demodulated signal; a second demodulating means for obtaining a data signal by performing multi-level discrimination on the demodulated signal; and a first reproducing means for reproducing the sub data signal from the data signal; Level determining means receives the data signal, determines the amplitude value of the composite modulated wave, and outputs a determination signal; and receives the data signal, controls the phase according to the sub data signal and the determination signal, and controls the main data. A demodulator comprising: second reproducing means for reproducing a signal. 3. a first modulating means for modulating a carrier wave with a main data signal having a first code transmission rate to obtain an orthogonal amplitude modulated wave; When modulating with a sub-data signal at a transmission rate, one is selected from a plurality of phase values according to the amplitude value of the orthogonal amplitude modulated wave, and the orthogonal amplitude modulated wave is phase-modulated with the selected phase value and complexed. a modulation device having a second modulation means for obtaining a modulated wave; a first demodulation means for obtaining first and second demodulated signals by quadrature phase detection of the composite modulated wave; second demodulation means for reproducing the sub-data signal from the data signal; and a second demodulation means for reproducing the sub-data signal from the data signal; and a second demodulation means for reproducing the sub-data signal from the data signal; a demodulating device having a level discriminating means for outputting the output; and a second reproducing means for receiving the data signal, controlling the phase according to the sub data signal and the discrimination signal, and reproducing the main data signal. Characteristic digital modulation and demodulation system.