JP3311773B2 - 4-phase PSK demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a four-phase PS for performing signal processing by identifying a four-phase PSK demodulated signal by an A / D converter.
More particularly, the present invention relates to a four-phase PSK demodulator that performs digital processing using a digital transversal equalizer or the like.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional four-phase PSK demodulator. In FIG. 6, reference numeral 11 denotes a quadrature detector, and this quadrature detector 11 converts an intermediate frequency signal (IF signal). It is detected and output as two orthogonal components. Numeral 12 denotes a variable gain type amplifier. The variable gain type amplifier 12 is provided with a four-phase PSK from the quadrature detector 11.
The amplitude of the demodulated signal is increased or decreased. An A / D converter 14 converts an analog demodulated signal of the variable gain amplifier 12 into a digital demodulated signal.

A variable gain amplifier 13 and an A / D converter 15 having similar functions are connected to the other of the quadrature detector 11. Reference numeral 16 denotes an equalizer, which performs a waveform equalization process on the output from each of the A / D converters 14 and 15 and outputs an I channel data signal and a Q channel data signal. It is.

Reference numeral 17 'denotes an automatic drift control logic circuit. The automatic drift control logic circuit 17' calculates a drift control signal from the output of the equalizer 16 and converts the drift control signal into an A / D converter. The drift amount of the input signal to each of the A / D converters 14 and 15 is controlled by feeding back to the input sides of the A / D converters 14 and 15. Reference numeral 18 'denotes an automatic gain control logic circuit. The automatic gain control logic circuit 18' calculates a gain control signal from the output of the equalizer 16, and uses the gain control signal to generate variable gain amplifiers 12, 13. To control the amplification factor.

Reference numerals 19, 20, and 23 to 26 denote low-pass filters, and reference numerals 21 and 22 denote capacitors. With the above-described configuration, the quadrature detector 11 detects the intermediate frequency signal and outputs it as two orthogonal components. One output is sent to the variable gain amplifier 12 via the low-pass filter 19, and the variable gain amplifier 12 Then, the amplitude of the four-phase PSK demodulated signal is increased or decreased. The A / D converter 14 converts the analog demodulated signal of the variable gain amplifier 12 into a digital demodulated signal via the capacitor 21.

Also, at the other output of the quadrature detector 11, a low-pass filter 20, a variable gain amplifier 1
3, the capacitor 22 and the A / D converter 15 perform the same operation. Next, the A / D converters 14 and 1 are equalized by the equalizer 16.
5 is subjected to a waveform equalization process to output an I-channel data signal and a Q-channel data signal.

In the automatic drift control logic circuit 17 ',
A drift control signal is calculated from the output of the equalizer 16 and the drift control signal is fed back to the input sides of the A / D converters 14 and 15 to thereby calculate the amount of drift for the input signals to the A / D converters 14 and 15. Control. The automatic gain control logic circuit 18 'calculates a gain control signal from the output of the equalizer 16 and controls the gains of the variable gain amplifiers 12 and 13 with the gain control signal.

FIG. 7 shows the identification area of the A / D converter and the four-phase PS.
FIG. 6 is a diagram illustrating a relationship with a K signal point. In FIG. 7, in consideration of the spread of the signal due to fading or the like, the four-phase PSK signal is compressed to half of the normal amplitude in order to secure the dynamic range of the A / D converter. Therefore, in FIG. 7, D0 is the polarity signal, D
2 is an error signal.

Normally, the automatic drift control logic circuit 1
7 'calculates a drift control signal using the error signal D2. That is, when the position of the signal point shifts upward, D2
Are both set to 1 to control to reduce the drift amount. Conversely, when the position of the signal point shifts downward, both D2 become 0 and control is performed so as to increase. Further, the automatic gain control logic circuit 18 'calculates the gain control signal by taking an exclusive logical OR (EXOR) of the polarity signal D0 and the error signal D2.
When the position of the signal point is widened, EXOR (D0, D2) becomes 0
And control is performed to reduce the amplification factor. Conversely, when the position of the signal point becomes narrow, EXOR (D0, D2) becomes 1
And control is performed to increase the amplification factor. Where E
XOR (D0, D2) means taking an exclusive logical loop of D0 and D1.

However, in the above case, in addition to the normal signal points indicated by the circles, the same calculation results are obtained at the positions of the squares, thereby having pseudo-stable points indicated by the squares.

[0011]

As described above, in the conventional four-phase PSK demodulator, in addition to the position of the normal signal point, there is a pseudo-stable point having the same operation result as that of the normal signal point. There is a problem that the control is not performed. SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and can identify a four-phase PSK demodulated signal in a steady and accurate manner by avoiding a pseudo-stable point in automatic drift control and automatic gain control. 4 phase PSK
An object is to provide a demodulator.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. The four-phase PSK demodulator shown in FIG.
It comprises a quadrature detector 1, a pair of variable gain amplifiers 2, 3, a pair of A / D converters 4, 5, an equalizer 6, an automatic drift control logic circuit 7, and an automatic gain control logic circuit 8. Have been.

Here, the quadrature detector 1 detects the intermediate frequency signal and outputs it as two orthogonal components, and the variable gain amplifiers 2 and 3 perform four-phase PSK demodulation from the quadrature detector 1. The A / D converters 4 and 5 convert the analog demodulated signals of the amplifiers 2 and 3 into digital demodulated signals, and the equalizer 6 controls the A / D conversion. It performs a waveform equalization process on the outputs from the devices 4 and 5, and outputs an I channel data signal and a Q channel data signal.

The automatic drift control logic circuit 7
By calculating a drift control signal from the output of the equalizer 6 and feeding back the drift control signal to the input side of the A / D converters 4 and 5, the input signal to the A / D converters 4 and 5 is calculated. To control the drift amount of
For this reason, the automatic drift control logic circuit 7
The first bit output of the / D converters 4 and 5 is D0, and the A / D
When the second bit output of the converters 4 and 5 is D1 and the third bit output of the A / D converters 4 and 5 is D2,

[0015]

(Equation 3)

Is calculated, and the calculation result is output as the drift control signal. Further, the automatic gain control logic circuit 8 calculates a gain control signal from the output of the equalizer 6 and uses the gain control signal to
3 is controlled by the automatic gain control logic circuit according to the following equation.

[0017]

(Equation 4)

Is operated, and the result of the operation is output as the gain control signal. by the way,
An OR gate circuit for calculating the logical sum of the second bit output of the A / D converters 4 and 5 and the third bit output of the A / D converters 4 and 5; A /
Second bit output of D converters 4, 5 and A / D converters 4, 5
AND gate circuit for calculating the logical product of the A / D converters 4 and 5 and the output of the OR gate circuit when the first bit output of the A / D converters 4 and 5 is 0. , 5
When the first bit output is 1, the selector selects the output of the AND gate circuit.

The above-mentioned automatic gain control logic circuit 8
An OR gate circuit for calculating the logical sum of the second bit outputs of the A / D converters 4 and 5 and the third bit outputs of the A / D converters 4 and 5, 2nd bit output and A
A NAND gate circuit that performs a logical product operation with the third bit outputs of the / D converters 4 and 5 and inverts the operation result;
When the first bit output of the D converters 4 and 5 is 0, the output of the OR gate circuit is selected. When the first bit output of the A / D converters 4 and 5 is 1, the output of the NAND gate circuit is selected. It can also be configured with a selector that performs this.

[0020]

In the above-described four-phase PSK demodulator of the present invention, the quadrature detector 1 detects the intermediate frequency signal and outputs it as two orthogonal components. Of a pair of variable gain amplifiers 2 and 3
The analog demodulated signals from the amplifiers 2 and 3 are converted into digital demodulated signals by a pair of A / D converters 4 and 5. Thereafter, the equalizer 6 performs a waveform equalization process on the output from each of the A / D converters 4 and 5 to output an I channel data signal and a Q channel data signal.

At this time, the automatic drift control logic circuit 7
Calculates the drift control signal from the output of the equalizer 6,
By feeding back the drift control signal to the input side of the A / D converters 4 and 5, the amount of drift of the input signal to the A / D converters 4 and 5 is controlled.
The automatic gain control logic circuit 8 calculates a gain control signal from the output of the equalizer 6 and controls the amplification factor of the amplifier with the gain control signal.

In the automatic drift control logic circuit 7, the first bit output of the A / D converters 4 and 5 is set to D0.
The second bit output of the A / D converters 4 and 5 is D1, and
When the third bit output of the D converters 4 and 5 is D2, the above equation (1) is calculated, and the calculation result is output as a drift control signal. Further, the automatic gain control logic circuit calculates the above equation (2) and outputs the calculation result as a gain control signal.

Note that the automatic drift control logic circuit 7
The second bit output of the A / D converters 4, 5 and the A / D converters 4,
And an OR gate circuit for calculating a logical sum with the third bit output of the A / D converters 4 and 5 and the AND of the second bit outputs of the A / D converters 4 and 5 and the third bit outputs of the A / D converters 4 and 5 Operate AN
When the first bit output of the D gate circuit and the A / D converters 4 and 5 is 0, the output of the OR gate circuit is selected. When the first bit output of the A / D converters 4 and 5 is 1, the output is selected. By including the selector for selecting the output of the AND gate circuit, the operation of the above equation (1) can be realized.

Further, the automatic gain control logic circuit 8
The second bit output of the A / D converters 4, 5 and the A / D converters 4,
And an OR gate circuit for calculating a logical sum with the third bit output of the A / D converters 4 and 5 and the AND of the second bit outputs of the A / D converters 4 and 5 and the third bit outputs of the A / D converters 4 and 5 When the first bit output of the A / D converters 4 and 5 is 0, the output of the OR gate circuit is selected, and the output of the A / D converters 4 and 5 is selected. When the output of the first bit is 1, a selector for selecting the output of the NAND gate circuit is provided.
The operation of the expression can be realized.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a four-phase PSK demodulator as one embodiment of the present invention. The four-phase PSK demodulator shown in FIG. 2 includes a quadrature detector 11 and a pair of variable gain amplifiers 1.
2, 13, a pair of A / D converters 14, 15, equalizer 1
6, automatic drift control logic circuit 17, automatic gain control logic circuit 18, low-pass filters 19, 20, 23 to
26 and capacitors 21 and 22.

Here, a quadrature detector 11, a pair of variable gain amplifiers 12, 13 and a pair of A / D converters 14, 1
5, equalizer 16, low-pass filters 19, 20, 23-
26 and the capacitors 21 and 22 are substantially the same as those of the related art, and the description of each of them has already been described, so that the description thereof will be omitted. The automatic drift control logic circuit 17 calculates a drift control signal from the output of the equalizer 16 and converts the drift control signal into A / D converters 14 and 15.
Of the input signals to the A / D converters 14 and 15 by feedback to the input side of the A / D converters 14 and 15. For this purpose, the automatic drift control logic circuit 17 is configured as shown in FIG. The OR gate circuit 31,
The circuit includes an AND gate circuit 32 and a selector 33.

Here, the OR gate circuit 31 is connected to the second bit output D1 of the A / D converters 14 and 15 and the A / D converter 1
The AND gate circuit 32 calculates the logical sum with the third bit output D2 of the A / D converters 14, 1 and 4.
5 and the third bit output D2 of the A / D converters 14 and 15 are operated by the logical AND of the first bit output D1 of the A / D converters 14 and 15.
When 0 is 0, the output of the OR gate circuit 31 is selected.
When the first bit output D0 of the / D converters 14 and 15 is 1, the output of the AND gate circuit 32 is selected.

Further, the automatic gain control logic circuit 18
The gain control signal is calculated from the output of the equalizer 16 and the gain control signals are used to control the amplification factors of the amplifiers 12 and 13. For this purpose, the automatic gain control logic circuit 18 is provided with a logic circuit shown in FIG. As shown in FIG.
The configuration includes an AND gate circuit 42 and a selector 43.

Here, the OR gate circuit 41 is connected to the second bit output D1 of the A / D converters 14 and 15 and the A / D converter 1
The NAND gate circuit 42 calculates a logical sum with the third bit output D2 of the A / D converters 4, 4, 15.
The selector 43 calculates the logical product of the second bit output D1 of the F.15 and the third bit output D2 of the A / D converters 14 and 15 and inverts the calculation result. , 15 select the output of the OR gate circuit 41 and output the first bit of the A / D converters 14, 15.
When the bit output is 1, the output of the NAND gate circuit 42 is selected.

With the above-described configuration, the quadrature detector 11, the pair of variable gain amplifiers 12, 13, the pair of A / D converters 14, 15, and the equalizer 16 perform the same operation as the conventional example. That is, the quadrature detector 11 detects the intermediate frequency signal and outputs it as two orthogonal components. One output is sent to the variable gain amplifier 12 via the low-pass filter 19, and the variable gain amplifier 12 Increase or decrease the amplitude of the PSK demodulated signal. The A / D converter 14 converts the analog demodulated signal of the variable gain amplifier 12 into a digital demodulated signal via the capacitor 21. The low-pass filter 20, the variable gain amplifier 13, the capacitor 22, and the A / D converter 15 perform the same operation on the other output of the quadrature detector 11. Next, the equalizer 16 performs a waveform equalization process on the outputs from the A / D converters 14 and 15 to output an I-channel data signal and a Q-channel data signal.

At this time, the automatic drift control logic circuit 1
In step 7, a drift control signal is calculated from the output of the equalizer 16 and the drift control signal is converted to A / D converters 14 and 15.
Of the input signal to the A / D converters 14 and 15 is controlled by feedback to the input side. That is, the automatic drift control logic circuit 17
In the OR gate circuit 31, the A / D converters 14, 15
Of the second bit output D1 of the A / D converters 14 and 15 and the third bit output D2 of the A / D converters 14 and 15,
The logical product of D1 and D2 is calculated by the D gate circuit 32, and the selector 33 outputs the output of the OR gate circuit 31 when the first bit output D0 of the A / D converters 14 and 15 is 0. Select, and when D0 is 1, AND gate circuit 32
Select the output of

Thus, in the automatic drift control logic circuit 17, the following equation is obtained.

[0033]

(Equation 5)

The drift control signal is output from the selector 33 to the A / D converters 14 and 15. The automatic gain control logic circuit 18 calculates a gain control signal from the output of the equalizer 16 and controls the amplification factors of the amplifiers 19 and 20 with the gain control signal. That is, in the automatic gain control logic circuit 18, the OR gate circuit 41 calculates the logical sum of D1 and D2,
The result of the logical product of D1 and D2 is inverted by the D gate circuit 42, and the output of the OR gate circuit 41 is selected by the selector 43 when D0 is 0, and when the D0 is 1, the NAND gate circuit 42 is selected. Select the output of Thus, the automatic gain control logic circuit 18 uses the following equation:

[0035]

(Equation 6)

The gain control signal is output from the selector 43 to the amplifiers 19 and 20 by implementing the calculation of the above. It should be noted that the automatic drift control logic circuit 17 employs the above equation (3) as a means different from the circuit shown in FIG. 3 (either a hardware means, a software means or a firmware means). And a calculation result can be output as a drift control signal.

As the automatic gain control logic circuit 18, the above equation (4) may be implemented by means other than the circuit shown in FIG. 4 (in addition to hardware means, software means or firmware means). Good), and the result of the calculation can be output as a gain control signal. Equation (3) is calculated by the following equation.

[0038]

(Equation 7)

The above equation (4) can be simplified as follows.

[0040]

(Equation 8)

Since these equations can be simplified, these equations are calculated, the calculation result of equation (5) is output as a drift control signal, and the calculation result of equation (6) is calculated as a gain control signal. You may make it output. FIG. 5 is a diagram for explaining the automatic drift control signal and the automatic gain control signal.
By outputting the result of the calculation of the expression or the expression (5) as the drift control signal, it is understood that the drift control is performed only at the normal signal points, and the pseudo stable point can be avoided. In addition, it can be seen that by outputting the result of the operation of the expression (4) or the expression (6) as a gain control signal, the gain control is performed only at the normal signal points and the pseudo stable point can be avoided.

As described above, by avoiding the pseudo stable point in the automatic drift control and the automatic gain control,
The four-phase PSK demodulated signal can be steadily and accurately identified.

[0043]

As described in detail above, the four-phase PS of the present invention
According to the K demodulator, by avoiding the pseudo-stable point in the automatic drift control and the automatic gain control, the four-phase P
There is an advantage that the SK demodulated signal can be identified constantly and accurately.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing one embodiment of the present invention.

FIG. 3 is a block diagram showing a logic circuit for automatic drift control.

FIG. 4 is a block diagram showing a logic circuit for automatic gain control.

FIG. 5 is a diagram for explaining a drift control signal and a gain control signal.

FIG. 6 is a block diagram showing a conventional four-phase PSK demodulator.

FIG. 7 is a diagram showing a relationship between an identification area of an A / D converter and four-phase PSK signal points.

[Explanation of symbols]

 1,11 Quadrature detector 2,3,12,13 Variable gain amplifier 4,5,14,15 A / D converter 6,16 Equalizer 7,17,17 'Automatic drift control logic circuit 8,18 , 18 'Automatic gain control logic circuit 19, 20, 23 to 26 Low pass filter 21, 22 Capacitor 31, 41 OR gate circuit 32 AND gate circuit 33, 43 Selector 42 NAND gate circuit

────────────────────────────────────────────────── ─── Continued on the front page (56) References Patent 2861154 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00

Claims (2)

(57) [Claims] 1. A quadrature detector (1) for detecting an intermediate frequency signal and outputting it as two orthogonal components, and a pair of quadrature detectors for increasing and decreasing the amplitude of the four-phase PSK demodulated signal from the quadrature detector (1). Variable gain amplifier (2, 3)
And a pair of A / D converters (4, 5) for converting analog demodulated signals of the amplifiers (2, 3) into digital demodulated signals, and waveforms of outputs from the A / D converters (4, 5). An equalizer (6) for performing an equalization process and outputting an I-channel data signal and a Q-channel data signal is provided, and a drift control signal is calculated from an output of the equalizer (6) to calculate the drift. Automatic drift control logic circuit for controlling a drift amount of an input signal to the A / D converter (4, 5) by feeding back a control signal to an input side of the A / D converter (4, 5). (7) an automatic gain control logic circuit (8) for calculating a gain control signal from the output of the equalizer (6) and controlling the amplification factor of the amplifier (2, 3) with the gain control signal; Logic circuit for automatic drift control (7), the A / D converter of the first bit output of the (4,5) and D0, the A / D converter and the second bit output of the (4,5) and D1, the A / D
When the third bit output of the converter (4, 5) is D2,
The following equation And outputs the result of the operation as the drift control signal, and the automatic gain control logic circuit (8)
Is given by the following equation: , And outputs the calculation result as the gain control signal. 2. The automatic drift control logic circuit (8).
Is the second bit output of the A / D converter (4, 5) and the A / D
An OR gate circuit for calculating a logical sum with a third bit output of the converter (4, 5); a second bit output of the A / D converter (4, 5) and the A / D
An AND gate circuit for calculating a logical product with a third bit output of the converter (4, 5); and an OR gate circuit when the first bit output of the A / D converter (4, 5) is 0 An output of the A / D converter (4, 5) when the first bit output is 1, and a selector for selecting an output of the AND gate circuit. A logic circuit (9) outputs the second bit output of the A / D converter (4, 5) and the A / D
An OR gate circuit for calculating a logical sum with a third bit output of the converter (4, 5); a second bit output of the A / D converter (4, 5) and the A / D
A NAND gate circuit for calculating a logical product of the third bit output of the converters (4, 5) and inverting the result of the operation, and a first bit output of the A / D converter (4, 5) of 0 When the output of the A / D converter (4, 5) is 1, the selector selects the output of the NAND gate circuit when the first bit output of the A / D converter (4, 5) is 1. The four-phase PSK demodulator according to claim 1, wherein: