JPH03285434A - Demodulator - Google Patents

Abstract

PURPOSE:To reduce circuit scale and to prevent a characteristic from being degraded by providing a transversal equalizer to control the outputs of two analog/digital converters by a quadrant signal and an error signal and to output equalized data compensating interference between codes. CONSTITUTION:A transversal equalizer 7 obtains quadrant signals X1 and Y1 and error signals X3 and Y3 from a main data signal reproducing circuit 9. Based on these signals, equalized data D'p and D'q compensating the interference between codes included in demodulated data Dp and Dq are outputted to a sub data signal reproducing circuit 8 and the main data signal reproducing circuit 9. Since this transversal equalizer obtains a signal for preparing a tap control signal from the output of the main data signal reproducing circuit 9, a normal digital type transversal equalizer can be used. Therefore, all the processings after A/D converters 6 and 6' are turned to be digital and LSI can be realized. Further, the circuit scale can be reduced and the characteristic can be prevented from being degraded.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a demodulation device used in a digital modulation/demodulation system that compositely transmits a sub data signal using phase modulation on a main data line using orthogonal amplitude modulation. In particular, it relates to a demodulator with enhanced anti-fading characteristics.

(Prior Art) Quadrature amplitude modulation has become the mainstream of digital wireless transmission systems in recent years because of its high efficiency.

By the way, the present inventor has developed an orthogonal amplitude modulated wave modulated by the main data signal to have a 2α radian phase with the sub data signal, with the aim of efficiently transmitting the sub data signal in a composite manner on the main data line using orthogonal amplitude modulation. proposed a digital modulation/demodulation system (Japanese Unexamined Patent Publication No. 183648/1983).

This digital modulation/demodulation system will be explained below.

FIG. 7 is a signal arrangement diagram of a composite modulated wave obtained by ±α radian phase modulation of a 16-value orthogonal amplitude modulated wave.

16 signal points CIJ(i.

(j is an integer from 1 to 4) is converted into signal point AI or signal point BIJ by phase modulation of ±α radians using the sub data signal. From a complex modulated wave whose signal point is AIJ or BIJ,
The main data signal and the sub data signal are reproduced as explained below.

First, the complex modulated wave is quadrature-phase detected, and the demodulated output P is the orthogonal shadow of the signal point AIJ or BIJ on the P and Q axes.
O, obtain the same Qo. Demodulation output PO1 and Q.

The sub data signal can be reproduced by logically operating the data obtained by multi-value discrimination at the discrimination level of ±3L and the data obtained by discrimination at the discrimination level of the origin position 0. In addition, "r phase synchronized circuit by the present inventor" (Japanese Patent Publication No. 58-
Demodulated output P is obtained using the circuits shown in FIGS. 7 and 9 described in Japanese Patent No. 698. , same Q. It is also possible to reproduce the sub data signal from.

The demodulated outputs Po and Qo are subjected to multi-value discrimination via +α radian phase shifter and -α radian phase shifter which are analog calculation circuits, and one of the obtained output data corresponds to the sub data signal obtained first. By selecting the main data signal, the main data signal can be reproduced. Since the identification margin of the sub data signal is smaller than that of the main data signal, if the code transmission speed of both data signals is the same, the code error severity of the sub data signal will be poor, and the signal error of the sub data signal will cause the main data signal to The reproduction of the data signal will also be erroneous. Therefore, by setting the code transmission rate of the sub data signal to an integer (m > 1/1/2) of the code transmission rate of the main data signal, the code error severity of the sub data signal can be reduced by the improvement effect of band limitation or the improvement effect of majority decision. In addition, if the value of α is increased, the bit error severity of the sub data signal will improve, but on the other hand, the code error severity of the main data signal will worsen, so There is a limit, which is about 0.16 radian in the case of 16 values.In this case, although it differs depending on the signal point, the C/N deterioration amount is about 6 dB with respect to the main data signal at the best point.16 values In this case, it is possible to reduce the value of m to about 8.

Using the digital modulation/demodulation system explained above, α
By appropriately selecting the values of and m, the sub data signal can be transmitted without deteriorating the bit error rate of the main data signal.

In addition, the inventor of the present invention designed the demodulator used in this system to be of a digital processing type and has a circuit configuration that can be integrated into an LSI, in view of the fact that one of the causes of characteristic deterioration is imperfections in the hardware. This is a proposal (Unexamined Japanese Patent Publication No. 63-1
93625).

(Problem to be Solved by the Invention) By the way, since there are various kinds of aging in the radio propagation path, transversal technology is needed to strengthen anti-fading characteristics and improve the deterioration of code error severity due to intersymbol interference. It is effective to use an equalizer.

However, as described above, the digital modulation/demodulation system proposed by the present inventor is a special system, so the problem is how to apply the transversal equalizer. In this case, it is desirable to employ a digital processing type transversal equalizer in order to eliminate the characteristic deterioration due to the aforementioned hardware imperfections and to enable reduction in circuit scale.

The present invention was made in view of such problems, and its purpose is to provide a demodulator for use in a digital modulation/demodulation system in which a sub data signal is transmitted in a composite manner using phase modulation on a main data line using orthogonal amplitude modulation. It is an object of the present invention to provide a demodulator that can enhance anti-fading characteristics and reduce the circuit scale.

(Means for Solving the Problems) In order to achieve the above object, a demodulator of the present invention has the following configuration.

That is, the demodulator of the present invention includes a quadrature phase detection circuit that performs quadrature phase detection on an input signal that is a composite modulated wave obtained by phase modulating a quadrature amplitude modulated wave modulated with a main data signal and a sub data signal; two analog-to-digital converters for multi-value identification of two demodulated outputs of the circuit, respectively, with an identification resolution of at least 2 bits more than the minimum number of bits necessary for discrimination of the main data signal;
and a sub-coefficient that receives the second equalized data and creates first coefficient data, performs a predetermined digital operation on the coefficient data and the first and second equalized data, and reproduces and outputs the sub-data signal. a data signal reproducing circuit; receives the first and second equalized data and the reproduced sub-data signal, creates second coefficient data from the reproduced sub-data signal; a main data signal reproducing circuit that performs a predetermined digital operation on the equalized data of No. 2, removes the sub data signal component, and reproduces and outputs the main data signal;
The error obtained from the output of the two analog-to-digital converters and the quadrant signal obtained from one of the outputs of the two analog-to-digital converters or the output of the main data signal regeneration circuit and the output of the main data signal regeneration circuit. The present invention is characterized by comprising: a transversal equalizer that is controlled by a signal and outputs the first and second equalized data that have been compensated for intersymbol interference.

(Function) Next, the function of the demodulator of the present invention configured as described above will be explained.

As is well known, a transversal equalizer compensates for intersymbol interference using a quadrant signal and an error signal, of which the error signal is obtained from the output of the main data signal reproducing circuit. Therefore, in the transversal equalizer, although the transmitted signal is a special complex modulated wave signal,
The operation is performed so that the reproduced main data signal, which is a demodulated data signal of a normal orthogonal amplitude modulated wave, is optimized. However, this means that the composite modulated wave is also optimized.

In short, the transversal equalizer used in the present invention is not a special one, but is a commonly used one, and therefore, a well-known digital processing type can be used. As a result, the analog-to-digital converter and subsequent components can be digitized, that is, integrated into an LSI, making it possible to reduce the circuit scale and prevent characteristic deterioration due to imperfections in the hardware.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a demodulation device according to an embodiment of the present invention. This embodiment device has a configuration for reproducing and outputting main data, evening signals, and sub data signals from the composite modulated wave shown in FIG. An example will be described below with reference to FIG. 7 as appropriate.

The input signal IN is a received signal converted to an intermediate frequency band, and as shown in FIG. 7, a 16-value orthogonal amplitude modulated wave modulated by the main data signal is ±α radian phase modulated by the sub data signal. It is a complex modulated wave. Therefore, the signal point is indicated by AIJ or BIJ in FIG. The signal point of the main data signal is CLI, but this signal point CIJ is P@
The two main data signals that define the position in the direction are X, , X2, and the two main data signals that define the position in the Q-axis direction are y,
, y2, and Xl and Y are the main data signals that determine the quadrant of the signal point C1. Note that the code transmission rate of the sub data signal is set to 1/m of the code transmission rate of the main data signal.

The input signal IN is amplified to a predetermined amplitude by an intermediate frequency amplifier 1, and is amplified by a voltage controlled oscillator (VCO) 2 by a quadrature phase detector 3.
Quadrature phase detection is performed using the output as the reference phase. Demodulation output P which is the detection output. , the same Qo is the signal point AIJ or the same BI
This is an orthogonal shadow of J onto the P and Q axes. Demodulation output P. , same Q
. are the baseband amplifiers 4 and 4, respectively. It is amplified to a predetermined amplitude by the analog-to-digital (A/D) converter 6. 6', the demodulated data D2. Same,
is converted to Demodulated data D2. Similarly, the greater the number of bits, the better the accuracy of subsequent signal processing, and in the case of 16 values, at least 4 to 5 bits are required.

The transversal equalizer 7 obtains a quadrant signal (X1+Yt) and an error signal (X3.Y3) from the main data signal reproducing circuit 9 in this embodiment, although the details will be described later (see FIG. 6).
Based on this, equalized data (D.

D9') is output to the sub data signal reproducing circuit 8 and the main data signal reproducing circuit N9.

The sub data signal reproducing circuit 8 includes a logic circuit and a digital arithmetic circuit. The logic circuit uses equalized data (
D, , Dq ), (first) coefficient data is output. The digital arithmetic circuit processes coefficient data and equalization data (D.

D,') are digitally operated to reproduce the sub data signal S. Specifically, it can be configured as shown in FIGS. 2(a) and 2(b), for example.

In FIG. 2(a), this sub data signal reproducing circuit is
A logic circuit 81 and two multipliers 82 . 83, a subtracter 84, and a majority decision circuit 85.

The logic circuit 81 receives main data signals Xl, X2 and Y1 . Equalized data D, ′ and D corresponding to Y2
The position of the signal point CIJ (values of f, j) is determined from the upper two bits of 9', and the coefficient data M, 1 is determined according to the determination result.
And M, 1 is outputted to the corresponding multipliers 82 and 83. This correspondence relationship is shown in FIGS. 3(a) and (b). FIG. 3(a) shows the signal point CIJ and the coefficient data (M, +
, Mqt) is an explanatory diagram showing the correspondence relationship with the absolute value of Mqt). Figure 3(b) shows signal point CIJ and coefficient data (M#1
．． FIG. 3 is an explanatory diagram showing the correspondence relationship between the polarity of MQi) and the polarity of MQi.

When signal point CIJ is in the first or third quadrant (i
is 1 or 3, and j is 1 to 4), the multiplier 82. Same 8
3 is equalized data (DpD,') corresponding to signal point A,j
to the data corresponding to the vicinity of signal point All, signal point BIJ
Equalized data corresponding to (D.

Dq') into data corresponding to the vicinity of the signal point l3tt. As a result, the data string output by the subtracter 84 equivalently represents the analog amount of the sub data signal S, but the most significant bit of the data string is positive when the signal point AH is present, and positive when the signal point B is the signal point B.
When IJ, the data indicates that it is negative.

In addition, if the signal point CI is in the second or fourth quadrant (i is 2 or 4, j is 1 to 4), the multiplier 8
2. Since the same 83 converts the equalized data (D, ", Dq) corresponding to the signal point Azt or the same BIJ into data corresponding to the vicinity of the signal point B31 or the vicinity of the signal point A31, the subtracter 84 also The most significant bit of the data string to be output is data indicating that the signal point is positive when it is A or J, and negative when it is BIJ.Therefore, the most significant bit of the data string that is output from the subtractor 84 is positive. By checking whether the signal point is positive or negative, it can be determined whether the signal point is AIJ or Bl. In other words, the sub data signal S can be obtained.

Since the data string output speed of the subtracter 84 is equal to the code transmission speed of the main data signal, the subtracter 84 outputs 1 of the sub data signal S.
Output a data string m times for the code. Majority decision circuit 8
5 counts the most significant bit of the output of the subtracter 84 for m days, makes a majority decision, and outputs the decision result as a sub data signal S for m times.

This majority logic operation improves the bit error rate characteristics of the sub data signal S.

Next, the sub data signal reproducing circuit shown in FIG. 2(b) is constructed by removing the majority decision circuit 85 from the sub data signal reproducing circuit shown in FIG. Wave device (L
PF)87. It is configured by adding an A/D converter 88.

The data string output from the subtracter 84 is converted into an analog value by a D/A converter 86, band-limited by an LPF 87, and digitized by a 1-bit A/D converter 88 to become a sub data signal S. By limiting the band of the LPF 87, the bit error rate characteristics of the sub data signal S are improved. The band of the LPF 87 is set to around 1/m of the code transmission rate of the main data signal.

Next, the main data signal reproducing circuit 9 is also configured to include a logic circuit and a digital arithmetic circuit, similarly to the above-described sub data signal reproducing circuit 8. The logic circuit corresponds to the sub data signal S outputted by the sub data signal reproducing circuit 8 (second).
Output coefficient data. The digital arithmetic circuit calculates the equalized data (D, , D9) by digitally computing the coefficient data and the equalized data l'p, I)Q).
) removes the phase modulation component caused by the sub data signal S.

The most significant bit and the second bit of the two data obtained in this way are the main data signals (XI, Yl) and the same (X2.Y2), and the third bit is the error signal (Xs, Specifically, such a main data signal reproducing circuit 9 (Ys) can be configured as shown in FIG. 4, for example.

In FIG. 4, this main data signal regeneration circuit includes a delay circuit 91, a logic circuit 92, a multiplier 93, a multiplier 94,
It includes an adder 95 and an adder 96.

The delay circuit 91 delays the equalized data (Dp, D,). This delay time is the period from when the first equalized data (D2, Dq') used to obtain one code of the sub data signal S is input to the sub data signal reproducing circuit 8 until the sub data signal S
is set to the time at the beginning t of that code. With this setting, the main data signal reproducing circuit 9 receives one of the sub data signals S.
While the code is being input, the equalized data (D, , DQ') used to obtain the code is input to the multiplier (93, 94>) and the adder (95, 96).

The logic circuit 92 outputs coefficient data (M-2, M-2) having the relationship shown in FIG. 5 depending on whether the sub data signal S corresponds to the code point AIJ or the code point Bl. .

Digital operations by the multipliers (93, 94) and the adder (95°96) are performed by converting the addition result data of the adder (95°96) into D95. When expressed as D96, it can be written as follows.

However, when the value of the sub data signal S corresponds to the signal point AIJ, it takes the upper plus/minus sign, and when it corresponds to the signal point BIJ, it takes the lower plus/minus sign.

Equation (1) becomes an equation that rotates the vector (D,', Dq) corresponding to the signal point AIJ armpit or the same BIJ by +α radian or 1α radian, if the constant value coefficient (1/cosα) is ignored. Therefore, the equalized data (D,”
D, ) corresponds to signal point AIJ or signal point BIJ, data (D, ) corresponds to signal point AIJ or signal point BIJ.
95. D96) becomes data corresponding to signal point CIJ. Therefore, the data (D95°D96) is equalized data (
The data is obtained by removing the phase modulation component by the sub data signal S from D,',D,). Adder (95,
96) converts the upper 3 bits of the addition result data (D95. D96) into data signals (XI to X, , Y,
~Y3).

As explained above, by appropriately selecting the value of the ratio m between the code transmission rate of the main data signal and the code transmission rate of the sub data signal and the amount of modulation phase shift α by the sub data signal, the sub data signal can be reproduced. The code error rate characteristic of the sub data signal S reproduced by the circuit 8 can be sufficiently improved, and the main data signal reproducing circuit 9 extracts the component of phase modulation by the sub data signal S from the equalized data (D, , D, ). Since the main data signal is reproduced by removing the sub data signal S, its code error rate characteristics will not deteriorate due to phase modulation by the sub data signal S.

Next, the LPF 10 and the logic circuits 11 and 12 will be explained.

The error signal (X3.Y3) is sent to the A/D converter (6°6')
Since the signal represents the deviation of the input signal from the normal value, the output DC level of the baseband amplifier 4 is determined by the output of low-pass filtering the error signal X3 by the LPF 10, and the error signal Y,
By controlling the output DC level of the baseband amplifier 5 with the output obtained by low-pass filtering with LPFIO, it is possible to compensate for the drift of the DC component of the input signal of the A/D converter (6, 6'). . Regarding the operation of this DC drift compensation, the present inventor's "Demodulator" (Japanese Unexamined Patent Publication No. 5
8-101449).

The logic circuit 11 receives data signals X 1 , X S + Y
Intermediate frequency amplifier 1 with two signals obtained from 1 and Yl
By controlling the gain of the baseband amplifier 5 and the A/D converter 6. This is a circuit that maintains the input signal amplitude of 6' at a normal value, and its configuration and operation are described in the "Automatic Gain Control Circuit" by the present inventor (Japanese Patent Laid-Open No. 59-1
69256).

The logic circuit 12 is a circuit that controls the VCO 2 with signals obtained from the data signals (Xl, , X3, Yl, and Yl) to form a phase-locked loop. It is described in detail in Reproducing Circuit J (Japanese Unexamined Patent Publication No. 57-131151).

Now, for example, as shown in FIG. 6, the transversal equalizer 7 uses quadrant signals (Xl, Yt) and error signals (X
, Y 3) and tap control signal (D 9Rjl +D
ot11+ DqR+1. A logic circuit 71 for creating Dq+++) and real axis equalizers (72-1, 72-4) provided on the real axis side (D-p=, DqR) of the demodulated data (D, , D=+). ) and the imaginary axis side (Dp+, DQ+
) and the outputs of the imaginary axis equalizers (72-2, 72-3) and the real axis (DpH) equalizer 72-1 provided in the imaginary axis section (DpH).
p+) and the output of the equalizer 72-2 to obtain equalized data D.
, ', and the imaginary axis part (D, +
) The output of the equalizer 72-3 and the real shaft part (Do) equalizer 72-
4 and an adder 73-2 which forms and outputs equalized data DQ'.

The four equalizers have the same configuration except for the tap control signals, and all have three taps.

As shown in detail in the axis detail (Do) equalizer 72-1, input data is shifted one time slot at a time in three stages of shift registers (SR) 74-1 to SR 74-3. The output of 5R74-1, which is the front stage tap, becomes one input of multiplier 75-1, and the output of 5R74-3, which is the second stage tap, becomes one input of multiplier 75-2, but the output of 5R74-2, which is the main tap, becomes an input to the direct adder 75-3. The other input of the multiplier 75-1 is the tap control signal D1.
111-1, and the other input of the multiplier 75-2 is the tap control signal D pR41, which outputs an optimal amount capable of compensating for intersymbol interference to the adder 75-3. The output of the adder 75-3 becomes one input of the adder 73-1. Note that 5R74-2 does not function as a mainter knob, but since this function is possessed by intermediate frequency amplifier 1, it is omitted in real axis section equalizer 72-1.

As is clear from the above explanation, in this transversal equalizer, the transmitted signal is a special composite signal.
A signal for creating a tap control signal is obtained from the output of the main data signal reproducing circuit 9, and the reproduced main data signal, which is demodulated data of a normal orthogonal amplitude modulated wave, is optimized, and as a result, the composite modulated wave is also optimized. As a result, an ordinary digital transversal equalizer can be used.

Therefore, all processing after the A/D converter (6, 6') is digital processing, making it possible to implement LSI, reducing the circuit scale and preventing characteristic deterioration due to hardware imperfections. becomes.

In the above explanation, both the quadrant signal and the error signal are obtained from the main data signal reproducing circuit 9, but only the quadrant signal is obtained when the output of the A/D converter (6, 6')<D,', D
, ') can be used for C.

(Effects of the Invention) As explained above, according to the demodulator of the present invention, since the transversal equalizer is provided, the orthogonal amplitude modulated wave modulated by the main data signal is phase-modulated by the sub data signal. This has the effect of providing a demodulator with good anti-fading characteristics in a digital modulation/demodulation system for complex modulated waves. Further, the transversal equalizer is not a special one, and a commonly used transversal equalizer can be used, so a well-known digital type can be used.

Therefore, the analog-to-digital converter and subsequent parts can be digitized, that is, integrated into an LSI, which has the effect of reducing the circuit scale and preventing characteristic deterioration due to imperfections in the hardware.

[Brief explanation of drawings]

FIG. 1 is an elliptic block diagram of a demodulator according to an embodiment of the present invention, and FIGS.
A block diagram of two configuration examples, FIG. 3 (a>(b) shows the relationship between the signal point CIJ, which is the input/output of the logic circuit in the sub data signal reproducing circuit shown in FIG. 2, and the coefficient data (Mpl, M, I). 4 is a configuration block diagram showing an example of the main data signal reproducing circuit, and FIG. 5 shows signal points (AI
J. BIJ) and coefficient data (M-2, M-2>; FIG. 6 is a block diagram showing an example of a transversal equalizer; FIG. It is a signal arrangement diagram of a complex modulated wave subjected to radian phase modulation. 3... Quadrature phase detector, 6, 6'...
・A/D converter, 7...Transversal equalizer, 8...Sub data signal regeneration circuit, 9...
...Main data signal regeneration circuit, 71...Logic circuit, 72-1゜72-4...Real axis equalizer, 72-2.72-3... ...Imaginary axis equalizer,
73-1.73-2.75-3...adder,
74-1 to 74-3...Shift register,
75-1.75-2... Multiplier, 81...
...Logic circuit, 82.83... Multiplier, 84
・・・・・・Subtractor, 92・・・Logic circuit,
93°94... Multiplier, 95.96...
...Adder.

Claims (1)

[Claims] a quadrature phase detection circuit that performs quadrature phase detection on an input signal that is a composite modulated wave obtained by phase modulating a quadrature amplitude modulated wave modulated by the main data signal with the sub data signal; two analog-to-digital converters for multi-value discrimination, each with a discrimination resolution of at least 2 bits more than the minimum number of bits required for discrimination of the main data signal; a sub-data signal reproducing circuit that generates coefficient data of 1, performs a predetermined digital operation on the coefficient data and the first and second equalized data, and reproduces and outputs the sub-data signal; 2 equalized data and the reproduced sub-data signal, the second equalized data is received from the reproduced sub-data signal.
a main data signal reproducing circuit that generates coefficient data, performs a predetermined digital operation on the coefficient data and the first and second equalized data, removes sub data signal components, and reproduces and outputs the main data signal. and a quadrant signal and a main data signal obtained from the output of the two analog-to-digital converters or the output of the main data signal reproducing circuit; a transversal equalizer that is controlled by an error signal obtained from the output of a reproducing circuit and outputs the first and second equalized data that have been compensated for intersymbol interference; .