JPS59139752A - Phase comparison type soft deciding circuit - Google Patents

Abstract

PURPOSE:To avoid the erroneous decision due to the level fluctuation of a received signal or an error of the reference voltage level of an A/D converter, by obtaining a soft decision output by means of combinations of phase wave detection output of the received signal. CONSTITUTION:A received signal ''1'' or ''0'' is supplied in parallel to each multiplier 15 and multiplied by soft deciding carriers 14-1-14-(2N-1) of different phases which are produced on the basis of a reference carrier 12 to be supplied to a comparator 17 via each LPF 16. Each comparator 17 compares an input signal with zero level and transmits a phase wave detection output to each corresponding soft deciding carrier. A logical circuit 18 decides the phase of a received signal based on the combination of outputs of each comparator 17 with the timing of a sampled pulse 7 and then performs decoding by a desired coding method. Thus a soft dicision outut signal 20 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a soft-decision circuit that performs demodulation and soft-decision of a received signal whose carrier signal is phase-modulated by digital data.

Soft decision means that the demodulated signal is determined to be “1” depending on a certain reference value.
'or' is a concept for hard decisions that are determined to be 0#, and by determining how close the temperature control signal is to 1, for example, whether it is 0.7 or 0.9, 1, vinegar,
The purpose is to determine how close the received signal is to the original signal. The soft decision result is used, for example, as an input signal to an error correction circuit.

FIG. 1 is a block diagram showing an example of a conventional soft decision circuit. That is, the carrier is phase-modulated by the transmission data, sent out to the transmission path, and inputted to the received signal input terminal 1. The received signal having the information of "θ" or J" is multiplied by the reference carrier wave 2 for demodulation in the multiplier 3 and the phase is detected. That is, the output signal of the multiplier 3 is the phase of the received signal and the reference carrier wave 2. The demodulated signal becomes a demodulated signal whose level and polarity correspond to the phase difference between the demodulated signal and the demodulated signal.
Noise components are removed and averaged by the PF) 4, the voltage level is adjusted by the DC amplifier 5, and the voltage level is adjusted by the analog-to-digital converter (A/D converter) 6 and output as a digital value. That is, the analog-to-digital converter 6 samples the output of the DC amplifier 5 using the sampling pulse 7 at the maximum timing of 8/N,
By comparing this with several reference levels, the phase information of the received signal is converted into digital values that are further subdivided between 0 and 1 and output. The digital value is logically converted by the soft-decision encoding logic circuit 8 according to a desired encoding method and outputted to the soft-decision output terminal 9. In the conventional circuit described above, linearity is required for both the amplitude characteristics and the two phase characteristics in order to prevent errors from occurring in the soft decision results due to distortion of the low-pass filter 4 and the DC amplifier 5. Furthermore, it has many drawbacks, such as the fact that gain adjustment corresponding to level fluctuations in the received signal is essential in order to prevent judgment errors caused by level fluctuations in the received signal. Particularly in burst mode TDMA, etc., there is a problem in that gain adjustment is difficult because there are variations in reception level between burst signals forming each channel. Further, an error in the reference voltage of the A/D converter also causes an error in the determination result.

An object of the present invention is to solve the above-mentioned conventional drawbacks and provide a phase comparison type soft decision circuit that does not make erroneous decisions due to level fluctuations of received signals, errors in the reference voltage level of the A/D converter, etc. It's about doing.

The determination circuit of the present invention is a soft decision circuit that determines how close a received signal in which a carrier signal is phase-modulated by digital data is to an original signal. Alternatively, a soft-decision carrier generation circuit that generates a soft-decision carrier wave with a variable phase is provided, and the received signal is phase-detected by the plurality of soft-decision carrier waves, and a soft decision is made based on a combination of phase detection outputs. It is characterized by getting the way out.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing a first embodiment of the present invention, and shows a configuration example of a non-feedback comparison type soft decision circuit that performs a 2N-value soft decision on a received signal of a two-phase PSK signal. In other words, 1" or "θ input from reception signal input terminal 1
'' is input in parallel to a plurality of multipliers 15. Each multiplier 15 receives a plurality of signals having slightly different phases generated by a soft-decision carrier generation circuit 13 based on a reference carrier 12. Soft decision carrier waves 14-(1) to 14
-(2N-1) are respectively supplied. Each of the plurality of multipliers 15 multiplies the input signal by the soft-decision carrier wave, and each output signal is inputted to the comparator 17 through the low-pass filter 16. Each comparator 17
compares each input signal with the 0 level and outputs it as a phase detection output of the received signal for the corresponding soft decision carrier. For example, the phase detection output of the comparator 17 is positive for soft-decision carriers (there are multiple) with a phase difference of less than 1 with respect to the reference carrier 12, and for soft-decision carriers with a phase difference of more than - In other words, if the phase detection output of the comparator 17 is negative, it is determined that the phase of the received signal and the phase of the reference carrier wave 12 completely match. Therefore, by combining the outputs of the plurality of comparators 17, it is possible to determine how close the received signal is to the original signal. Based on the combination of phase detection outputs of 2N-1 comparators 17, it is possible to express the phase of the received signal in 2N stages. The logic circuit 18 determines the phase of the received signal based on the combination of the outputs of the plurality of comparators 17 at the timing of the sampling pulse 7, and selects a desired encoding method (for example, binary representation).
The soft decision output signal 20 is encoded and outputted as a soft decision output signal 20.

This embodiment has the advantage of not causing erroneous determination due to level fluctuations of the received signal, since it is possible to perform a soft decision on the phase of the received signal, which is not related to the level of the received signal.

FIG. 3 is a block diagram showing a second embodiment of the present invention that performs a binary soft decision on a two-phase PSK signal. In this case, the reference carrier wave 32 is input to the soft decision carrier generation circuit 33, and based on the reference carrier wave 32, variable phase soft decision carrier waves 34 having successively different phases are generated and output. The soft decision carrier generation circuit 33 is, for example, 2'4'8
It has a built-in phase shifter, and by combining these, the phase shifter of 2' 2:l:
It is possible to output a variable-phase soft-decision carrier 8 transmission wave 34 having a phase difference such as 4'2±-±-. These variable phase soft decision carrier waves 34 are sequentially outputted by timing pulses of the first to Nth steps supplied from the successive approximation register 38. For example, in the first step, a soft decision carrier wave with a phase of I is output, and in the second step, a carrier wave for soft decision with a phase of 2:l:
40 phase output. Is the output phase of the second step -+
- or 4-11 is determined depending on whether the phase detection output of the comparator 37 (described later) in the first step is "positive" or "negative." Similarly, in the third step, 2:l
: A soft-decision carrier wave with a phase of 4±100 is output. The multiplier 35 multiplies the soft-decision carrier wave 34 and the received signal, and the output of the multiplier 35 is filtered by a low-pass filter 36 to remove noise components. It is removed and input to comparator 37. The comparator 37 compares the input signal with the θ level to obtain phase information.
Determine whether it is positive or negative.

That is, a phase detection output using the soft-decision carrier wave 34 of the received signal is output.

The successive approximation register 38 sequentially sends the timing pulses of the 1st to N+1th steps to the soft decision carrier generation circuit 33, and makes a soft decision at each step.

The phase information of the received signal for the soft-decision carrier output from the soft-decision carrier generation circuit, that is, the phase detection output of the comparator 370, is stored in a built-in register.

In addition, according to the "positive" or "negative" of the phase information, the soft-decision carrier generation circuit issues a command to shift the phase of the soft-decision carrier by -(n=1゜n...N+1) in the next step. 33. Since n increases with each step, the phase shift width of the soft decision carrier 340 becomes finer with each step.Then, the output of the comparator 37 corresponding to each step is stored in the successive approximation register 38, and the first
The phase detection output corresponding to the step to the N+1th step is accumulated as phase information of the received signal. The phase information,
That is, the stored values of the phase detection outputs obtained by phase-detecting the received signal using a plurality of soft-decision carrier waves corresponding to each step are read out by the data speed sampling pulse 39 and sent to the soft-decision encoding logic circuit 40. Sent.

The soft-decision encoding logic circuit 40 instructs the soft-decision carrier generation circuit 33 to follow the desired digital encoding method (eg, binary code) for the input categorization.

In the second step, the phase of the received signal is detected by the carrier wave for soft phase decision described above, and the phase detection output is accumulated in the successive approximation register 38. Further, in the third step, an instruction is given to shift the phase by ±π/8 according to the sign of the phase information.

Repeat the above operation and in the final step π/2N+1
The received signal is phase-detected using a soft-decision carrier wave with a phase accuracy of radians. Therefore, by combining the phase detection outputs of each step accumulated in the successive approximation register 38, the phase information of the received signal can be determined with an accuracy of π/2 N radians. The phase information is sent out at the timing of the sampling pulse 39, and the soft-decision encoding logic circuit 40 logically converts the phase information into a desired digital code to provide a soft-decision output.

As described above, in the present invention, a received signal is phase-detected using soft-decision carrier waves having a plurality of different phases,
Since the configuration is configured to obtain the phase information of the received signal by combining the phase detection outputs, it is sufficient that the phase information is stored at the 0 volt level in the phase detection output (compared to the conventional method, it is easier to amplify the received signal. This has the effect of easing the requirement for linearity, and eliminating the need to adjust the gain of the amplifier in response to level fluctuations in the received signal.Furthermore, since no A/D converter is used, the accuracy of the reference voltage and power supply voltage is reduced. , it has many effects such as easing the requirement for stability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional soft decision circuit.
FIG. 2 is a block diagram showing the first embodiment of the present invention;
FIG. 4 is a block diagram showing a second embodiment of the present invention, and FIG. 4 is a time chart showing signals of various parts for explaining the operation of the second embodiment. In the figure, 1... Received signal terminal, 2... Reference carrier wave, 3, 15.35... Multiplier, 4, 16.36
...Low pass filter, 5...DC amplifier, 6...
・Analog-digital converter, 7, 39... Sampling pulse, 8.18.40... Soft-decision encoding logic circuit, 9
゜20.41...Soft decision output, 12,32...Reference carrier wave, 13.33...Soft decision carrier generation circuit, 14
-(1) to 14-(2-1)... Soft decision carrier wave, 1
7゜37... Comparator, 34... Soft decision carrier wave, 3
8...Successive approximation register. Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney Tosumune Sumita Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a soft-decision circuit that determines how close a received signal whose carrier signal is phase-modulated by digital data is to the original signal, it is used for soft-decision carrier waves that have multiple different phases based on a reference carrier wave or for soft-decision decisions that have a variable phase. It is characterized by comprising a soft-decision carrier generating circuit that generates a carrier wave, and obtaining a soft-decision output based on a combination of phase detection outputs obtained by phase-detecting the received signal using the plurality of soft-decision carrier waves. Phase comparison type soft decision circuit.