JPS60178757A - Digital soft decision demodulator - Google Patents

Abstract

PURPOSE:To improve the estimating accuracy of an original signal and to obtain a large error correction gain by using the result of soft decision as an input signal to be applied to an error correction circuit. CONSTITUTION:The input modulation signal fed from an input terminal 11 is quantized to 2<n>-1 levels by 2<n>-1 units of comparators 22 then outputted in the form of 2<n>-1 units of binary digital signals. The outputsof these comparators 22 are converted into n-bit outputs by a logical converting circuit 23. An input signal 26 with no noise, and an input signal 27 deteriorated by noise are sampled by a D type flip-flop 13 with a reference carrier wave to sampling timing 28. The signal 26 is not deteriorated by noise and therefore a soft decision output 11 is obtained with the timing 28. While a soft decision output 10 is obtained since the waveform of the signal 27 is deteriorated by noise. The level of quantization is shown by ''29'' fed at the right end of the figure.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention provides each time slot of a PSK signal with n bits) (
The present invention relates to a digital soft-decision demodulator that obtains a demodulated output (n is an integer of 2 or more).

<Prior Art> A demodulator for digital communication generally demodulates into one of two values, and is called a hard-decision demodulator.

FIG. 1 is a diagram for explaining a conventional digital hard-decision demodulator when the input modulation signal is a two-phase PSK signal. The input modulation signal from input terminal 11 is sent to comparator 1.
2, it is converted into a binary digital signal. The output of the comparator 12 is sampled by a D-type flip-flop 13 using the reference carrier wave as the sampling timing.

A reference carrier wave for this sampling is generated by a carrier wave regeneration circuit 14. The output of the D-type flip-flop 13 is identified by the identification circuit 15 as one of the two values using the reference clock and sent to the output terminal 16 as a hard decision output. A reference clock for this identification is generated by the clock recovery circuit 17.

This conventional hard-decision demodulator uses a D-type flip-flop 13 as a phase detector, and the D-type flip-flop 13 can instantaneously detect the phase of the input modulated signal during sampling. However, it is composed of digital elements, and has a structure suitable for miniaturization and LSI integration.

On the other hand, in satellite communications, error correction is often used to effectively utilize the power of the earth station or satellite, and in order to obtain a large error correction gain, it is necessary to perform a soft decision. is set to “0” by a certain reference level.
Alternatively, it is a concept for hard decision that determines "1", and how close the demodulated signal is to "1" or "0".
For example, it is determined as 08 or 02.

By using the soft decision result as an input signal to the error correction circuit, the accuracy of estimating the original signal can be improved and a large error correction gain can be obtained. However, the conventional digital demodulator having the configuration shown in FIG. 1 cannot perform soft decisions, and when error correction is applied, it has the disadvantage that a large error correction gain cannot be obtained.

A conventional digital soft-decision demodulator was constructed as shown in FIG. That is, in FIG. 2, when the input modulation signal is a two-phase PSK signal, the input modulation signal from the input terminal 11 is phase detected by the phase detector 18 using the reference carrier wave from the carrier wave regeneration circuit 13, and the phase detection output is The low-pass 7p5 filter 19 removes the high frequency component, and the differential amplifier 2
1. The differential amplifier 21 amplifies the phase detection output with a new bell switch. Its amplified phase detection output ld
A 2-H comparator 22 converts the signal into 2n level Ki signals, and a logic conversion circuit 23 converts the 2-1 comparator outputs into n-bit outputs. The output of the n-bit logic conversion circuit 23 is identified by n identification circuits 24 using the reference clock from the clock regeneration circuit 17, and the output terminal 25 is identified by n identification circuits 24.
An n-bit soft decision output is supplied to the

This conventional soft-decision demodulator uses analog elements such as a phase detector 18, a low-pass filter 9, and a differential amplifier 21, so there are many adjustment points, and it also requires miniaturization and LSI integration.
The disadvantage was that it was not suitable for standardization.

<Summary of the Invention> It is an object of the present invention to provide a digital soft-decision demodulator that is suitable for miniaturization and LSI implementation, and is capable of making soft decisions.

According to this invention, an input modulation signal is quantized to two levels by 2-1 comparators (n is an integer above 2), and a plurality of D-type flip-flops are connected to the comparators to sample the input using a reference carrier wave. A plurality of identification circuits that identify inputs using reference clocks are sequentially connected in cascade, and a logic conversion circuit that converts 2n-1 inputs into n-bit outputs is connected to a comparator and a D-type flip 7.
0, between the D-type flip-flop and the identification circuit, or on the output side of the identification circuit.

<Embodiment> FIG. 3 shows an embodiment in which the present invention is applied when the input modulation signal is a two-phase PSK signal. The input modulated signal from the input terminal 11 is quantized to 2-level by 2-1 comparators 22 and output as 2n-1 binary digital signals.

These 2-1 comparator outputs are converted into n-bit outputs by the logic conversion circuit 23, and the n-bit outputs are sent to the carrier wave recovery circuit in the n D-type flip-flops 13. The D-type flip-flop 13 operates as a phase detector, and the phase difference with respect to the reference carrier at the time of sampling the input modulation signal is quantized into n bits. It is instantaneously detected as an output by the D-type flip-flop 13.Therefore, similarly to the conventional hard-decision post-encoder shown in FIG. No filter is required.

The n-bit phase detection output from the D-type flip-flop 13 is discriminated by n discriminators 24 using the reference clock generated by the clock recovery circuit 17 as a discrimination timing. Since the output of the D-type flip-flop 13 is quantized to n bits, the discriminator 24 obtains an n-bit soft-decision demodulated output. The discriminator 24 can also be constructed from a D-type flip-flop.

Figure 4 is a diagram for explaining the constant demodulation output of 2(4) when the input signal is 2-phase PSK and 2-bit soft decision. 26. The input signal (-example) 27 degraded by noise is sampled by the D-type flip-flop 13 in FIG.
Since there is no deterioration due to noise, sampling timing 2
8, a soft decision output (11) is obtained, but since the waveform of the input signal 27 is degraded due to noise, a soft decision output (10) is obtained. The number 29 at the right end of FIG. 4 indicates the quantization level.

In the case of an input modulated signal or a 4-phase PSK signal, two reference carrier waves having phases of 90 degrees are required.

Therefore, the reference carrier wave is used as the sampling timing, the n D-type flip-flops 13 sampling the n-bit output of the logic conversion circuit 23 and the reference clock are used as the identification timing, and the outputs of the n D-type flip-flops in the above □ are used as the identification timing. By preparing two sets each of n identification circuits and sampling these two n D-type flip-flops at timings that are 90 degrees out of phase with respect to the reference carrier frequency, the input modulated signal is P.S.
In the case of No. K18, soft judgment A-char tone is also possible.

FIG. 5 shows another embodiment of the present invention in which the input modulation signal is two-phase PSK, and as will be understood by comparing this with the embodiment of FIG. The output is sampled by a 2-11 D-type flip-flop 3 using the reference carrier as the sampling timing.
The 2-1 outputs of the D-type flip-flop 13 are converted into n-bit outputs by the logic conversion circuit 23. The output of the logic conversion circuit 23 is identified by the identification circuit 24 using the reference clock. Logic conversion circuit 2 in the embodiment of FIG. 3
3 and the D-type flip-flop 13 are interchanged in order.

FIG. 6 shows yet another embodiment of the invention in which the input modulation signal is two-phase PSK. In this case, the logic conversion circuit 23 and the identification Dl circuit 4 in the embodiment of FIG. 5 are different from each other.

Effect〉 Above explanation 1. According to the present invention, a soft-decision demodulator that can obtain an error correction gain as large as error correction when applying error correction can be constructed entirely using digital elements, and in particular, There is a new contribution of this invention in terms of miniaturization and LSI.In the embodiments shown in Fig. 3, Color 5, and Schiff Fig. 6, the one shown in Fig. 6 has a larger scale of hardware; One that operates at a high speed stage is obtained.The one shown in FIG. 3 has the following characteristics:

Figure 7 is a characteristic diagram in which the effect of soft decision when this invention is applied was confirmed through experiments. The modulation method is 2-phase PS
K, the quantization level is 4 (n=2), the horizontal axis is the SN ratio Eb/No (dB) per bit in the figure, the vertical axis is the error rate, the theoretical curve of error rate 31, error correction by hard decision Error rate experimental curve 32 when applying Error rate curve 3 when applying error correction using 2-bit soft decision according to the present invention
3 is shown.

Note that Viterbi decoding with a convolutional coding rate of 1/2 and a constraint length of 7 was used for error correction. Hard decision error rate curve 32
As can be seen by comparing the soft decision error rate curve 7<x33, for example, when the quantization level is 4, the error rate at 10 points is approximately 6.7 dB for curve 32 and approximately 5.5 dB'' for curve 33.
It has been experimentally confirmed that a soft decision gain of approximately 1.2 dB can be obtained because of c, and the effectiveness of the present invention has been demonstrated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional hard decision demodulator, FIG. 2 is a block diagram showing a conventional digital soft decision demodulator,
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is an explanatory diagram of the soft-format printer and adjustment output according to the invention, and FIGS. 5 and 6 are block diagrams showing other embodiments of the invention, respectively. 7 are explanatory diagrams of the effect of soft decision according to the present invention. 11: Input terminal, 13: D-type flip-flop, 14:
Carrier wave regeneration circuit, 17: Clock regeneration circuit, 22: Comparator, 23: Logic conversion circuit, 24: Identification circuit, 25
: Soft decision output terminal. 71 Figure 3 Figure '71'75 Kasumi I76i 777 Figure Eb/No (dB)

Claims (1)

[Claims] (1) In a demodulator that obtains a soft-decision demodulated output of Qn (n is an integer of 2 or more) bits from the input modulation signal, 2-1 comparators that quantize the input modulation signal to 2n levels;
A plurality of D-type flip-flops, which are also arranged at a later stage and sample each of their inputs with a reference carrier wave, and a plurality of D-type flip-flops, which are arranged at a later stage than these D-type flip-flops, and whose respective inputs are sampled by a reference clock. between the identification circuit and the comparator and the above-mentioned flip-flop, or between the above-mentioned flip-flop and the above-mentioned identification circuit;
Alternatively, it is placed after the above identification circuit and inputs 2-1 inputs to n.
A digital soft-decision demodulator that is similar to a logic conversion circuit that converts into bit output.