JPH098854A - Multilevel fsk receiver - Google Patents

Abstract

PURPOSE: To improve reception sensitivity by changing threshold voltage at the time of judging a bit in accordance with transmitting speed information on a received multilevel FSK signal on the multilevel FSK receiver of digital radio communication. CONSTITUTION: In a bit judgment means 102, a threshold setting means 105 sets threshold voltage in accordance with transmitting speed information extracted by a transmitting speed information extraction means 104 and supplies it to the bit judgment means 102 at the time of judging the demodulation output of the multilevel FSK signal 100 outputted from a demodulation means 101. Thus, an optimum bit judgment threshold corresponding to the transmitting speed of the multilevel FSK signal can be set and reception sensitivity at respective transmitting speeds improves.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a multilevel FSK receiver for digital radio communication.

[0002]

2. Description of the Related Art With the rapid increase in demand for wireless communication in recent years, the communication speed has been increased, and multi-valued is also used from the viewpoint of effective use of frequency bands. Further, in order to effectively use the communication capacity of the communication channel, the transmission speed is made variable, and when the communication capacity is small, the transmission speed is slowed down to improve the receiving sensitivity, and when the communication capacity is large, the transmission speed is increased. Etc. are adopted. As a configuration of such a multi-level FSK receiver whose transmission speed is variable, for example, a configuration described in US Pat. No. 5,311,554 is known. Hereinafter, a conventional multi-level FSK receiver will be briefly described with reference to FIG. 9 using a four-level FSK receiver as an example.

In FIG. 9, the 4-level FSK signal 900 has a component outside the reception band removed by a bandpass filter 901, and a local signal output from an oscillator 902 and a mixer 903.
In the intermediate frequency signal (IF signal). The IF signal is converted into a number of pulse waves proportional to the frequency by the pulse counting circuit 904, the high frequency component is removed by the low pass filter 905, and a voltage proportional to the frequency is obtained. In the bit determination circuit 906, 3
In the two comparators 907, 908 and 909, the resistors 910 and
The magnitude comparison with the threshold voltage divided by 911, 912, and 913 is performed, the four-value determination circuit 914 determines the four values, and the bit data is obtained. At this time, the threshold value for bit determination is generally set to the middle of each voltage corresponding to the demodulated output of each symbol.

If the configuration of FIG. 9 receives four-valued FSK signals at a plurality of transmission rates, the band limiting filter 901
By switching the cutoff frequency of the low-pass filter 905 according to the transmission speed, it is possible to perform reception with substantially good sensitivity.

[0005]

However, the above-mentioned conventional configuration has the following problems when receiving multi-level FSK signals of a plurality of transmission rates.

FIG. 10A is a frequency distribution of peak values of the output signal of the low pass filter 905 of the receiver shown in FIG. Due to the influence of noise, the distribution spreads with respect to the original peak value, and the spreading way is biased near the center voltage Vo. This is because the frequency distribution of the demodulation output of the noise component is reduced by the band limitation by the band pass filter 901 and the low pass filter 905, and the amplitude distribution corresponding to the high frequency component decreases.
This is because it is biased toward the center voltage Vo side as shown in FIG. The bias of the frequency distribution changes the transmission rate of the four-level FSK signal, and the band pass filter 901 and the low pass filter 905.
It changes when the cutoff frequency of is changed.

For example, when the transmission rate of the four-level FSK signal is set low and the pass bands of the band pass filter 901 and the low pass filter 905 are narrowed, the frequency distribution of the demodulation output of the noise component is as shown in FIG. 11 (b). And the frequency distribution is further biased to the Vo side. Therefore, the frequency distribution of the peak value of the demodulated output of the four-level FSK signal also becomes as shown in FIG.

Here, when bit determination is performed from the demodulation output of the frequency distribution as shown in FIG. 10 (a) or FIG. 11 (a), the optimum value of the threshold value intersects the frequency distribution of each symbol. It becomes a value. Therefore, when the transmission rate of the four-level FSK signal changes, the optimum bit determination threshold value changes. Therefore, in order to perform the optimum bit determination, it is necessary to change the threshold value according to the transmission rate.

The present invention solves the above-mentioned conventional problems, and improves the receiving sensitivity by changing the threshold value for bit determination according to the transmission rate information of the received multi-level FSK signal. With the goal.

[0010]

To achieve this object, a multilevel FSK receiver of the present invention receives and demodulates a multilevel FSK signal and outputs a voltage proportional to the instantaneous frequency of the multilevel FSK signal. Demodulating means, a bit determining means for performing a bit determination of the demodulated output using a threshold value, a decoder for extracting control information and transmission information from the bit determination output, and a transmission rate information in the control information It has a transmission rate information extracting means for outputting and a threshold setting means for setting a threshold voltage for bit determination.

According to the present invention, the multi-level FSK signal is a multi-level FSK signal containing error correction information, the decoder is an error correction means, and a bit error rate (hereinafter referred to as BER) for each symbol of the multi-level FSK signal. ) Calculating means for calculating BER,
The control information and the transmission information are extracted from the bit data after the error correction, and the threshold value setting means is constituted by the information extracting means.
The threshold voltage may be set using the transmission rate information and the BER calculation result for each symbol.

The present invention also relates to an A / D conversion circuit for converting the demodulated output into a digital signal, a digital bit synchronizing means for obtaining bit timing from the digitized demodulated output and outputting a timing signal, and a timing signal. At the time of bit determination for each symbol of the multi-level FSK signal by using a digital threshold value determination means for digitally determining the bit of the demodulated output and the value of the digital signal at the time of the bit determination and the bit data after error correction. And a multi-valued FS for calculating a histogram of digital values of
It may be configured to have transmission rate information of the K signal and threshold setting means for setting an optimum bit determination threshold from a histogram for each symbol.

[0013]

According to the present invention, the multi-valued F by the demodulating means is constructed by the above construction.
The SK signal is demodulated, a voltage proportional to the instantaneous frequency of the multi-level FSK signal is output, bit determination is performed using the threshold voltage in the bit determination means, and control information and transmission information are determined in the decoder from the determined bit data. Extract. Transmission rate information is extracted from the output control information by the transmission rate information extracting means and supplied to the demodulating means and the threshold setting means, and the threshold setting means sets the threshold voltage according to the transmission rate information. However, by supplying it to the bit determination means, it is possible to improve the reception sensitivity of the received multi-level FSK signal at each transmission rate.

According to the present invention, the demodulation means demodulates the multi-level FSK signal containing redundant error correction information, the bit data bit-judged by the bit judgment means is error-corrected by the error correction means, and after correction. The control information and the transmission information are extracted from the bit data of
The BER calculation means calculates the BER for each symbol of the multi-level FSK based on the position information of the error-corrected bit data output from the error correction means and the error-corrected bit data. In the setting means, the threshold voltage is set in accordance with the transmission rate information, and the threshold is finely changed so that the BER of each symbol becomes uniform without any deviation, so that each of the multi-valued FSK signals to be received is changed. It enables to improve the receiving sensitivity at the transmission speed.

According to the present invention, the demodulation output of the demodulation means is converted into a digital signal by the A / D conversion circuit, and the timing signal is converted into a digital threshold value determination means by bit synchronization with the demodulation output by the digital bit synchronization means. The digital threshold value judging means digitally judges the bit in accordance with the timing signal, and the histogram calculating means uses the digital value at the time of the bit judgment and the bit data after the error correction to obtain the multi-valued FSK signal. By calculating a histogram of digital values at the time of bit determination for each symbol and setting an optimum bit determination threshold from the histogram for each symbol in the threshold setting means, each transmission of the multi-valued FSK signal to be received. It enables to improve the receiving sensitivity at speed.

[0016]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the essential parts of a multilevel FSK receiver according to the first embodiment of the present invention.

In FIG. 1, 100 is a multilevel FSK signal, 101
Is a demodulation means for demodulating the multi-valued FSK signal based on the transmission rate information and outputting a voltage proportional to the instantaneous frequency of the multi-valued FSK signal 100. Means, 103 is a decoder for extracting control information and transmission information from bit data and outputting the information.
4 is a transmission rate information extracting means for extracting and outputting the transmission rate information from the control information, and 105 is a threshold setting means for setting and outputting a threshold voltage for bit determination based on the transmission rate information. Is.

In the multi-level FSK 100, for example, control information or the like is transmitted at a constant transmission rate at predetermined time intervals, and at other times, it is transmitted at the transmission rate declared in the immediately preceding control information. It is assumed that it is a four-valued FSK.

The bit decision means 102, as shown in FIG. 2, for example, has an absolute value circuit 201 for outputting an absolute value voltage centered on the bias voltage of the input signal, and comparison circuits 202, 20.
3, a bit synchronization circuit 204 that outputs a timing signal by bit synchronization from the output signal of the comparison circuit, and a latch circuit that latches and outputs the input signal based on the timing signal
205 and a bias voltage source 206.

The threshold value setting means 105 is, for example, as shown in FIG.
As shown in, a reference voltage source 207 that outputs a reference voltage that serves as a reference when setting a threshold value, and a plurality of preset voltages that are based on the reference voltage are switched and output according to a control signal. Voltage switching means 208 and switching control means for outputting a control signal according to transmission speed information
209 and.

The operation of the multi-valued FSK receiver (here, a four-valued FSK receiver as an embodiment) configured as described above will be described below.

First, the demodulation means 101 receives the 4-valued FS.
The K signal 100 is demodulated and a voltage proportional to the instantaneous frequency is supplied to the bit determining means 102. The bit determination means 102 determines the bit determination of the demodulation output of the demodulation means 100 by the 4-value FSK signal 1
The determination is performed based on the determination of the variation direction (sign determination) of the instantaneous frequency with respect to the carrier frequency of 00 and the variation width (amplitude determination).

In the amplitude judgment, the absolute value circuit 201 outputs the absolute value voltage centered on the bias voltage of the demodulation output signal, and the comparison circuit 202 outputs the comparison result with the threshold voltage. In the sign determination, the comparison circuit 203 outputs the comparison result with the bias voltage supplied from the bias voltage source 206.

In the bit synchronization circuit 204, the comparison circuits 202, 20
Based on the comparison result in 3, the demodulation output signal is bit-synchronized and the timing signal is supplied to the latch circuit 205. In the latch circuit 205, based on the timing of the timing signal supplied from the bit synchronization circuit 204, the comparison circuit 20
The amplitude determination result by 2 and the code determination result by the comparison circuit 203 are latched and supplied to the decoder 103 as 2-bit data.

In the decoder 103, the control information 106 and the transmission information 1 are extracted from the bit data obtained by the bit determining means 102.
07 and are extracted and output. The transmission rate information extraction means 104 extracts the transmission rate information 108 from the control information 106 output from the decoder 103, and demodulates the means 101 and the threshold value setting means 10.
Supply to 5.

Voltage switching means 2 of threshold value setting means 105
In 08, a plurality of threshold voltages are set in advance on the basis of the reference voltage output from the reference voltage source 207, and the switching control means 209 operates in accordance with the control signal output based on the transmission speed information 108. The threshold voltage is switched and supplied to the bit determining means 102.

As described above, according to this embodiment, by using the information of the transmission rate of the subsequent signal included in the control signal transmitted at the constant transmission rate at each predetermined time,
It is possible to improve the reception sensitivity by changing the threshold voltage in bit determination.

In this embodiment, the demodulation output signal output from the demodulation means 101 is directly supplied to the bit determination means 102. However, the present invention is not limited to this. For example, the center voltage of the demodulation output signal is essentially the center. If there is a possibility that an error occurs with respect to the bias voltage to be obtained, a coupling circuit for removing this error voltage is provided in the subsequent stage of the demodulation means 101, and the output signal of the coupling circuit is determined by the bit determination means 102. It may be configured to supply to.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a main part of a multilevel FSK receiver according to the second embodiment of the present invention.

3 is different from the configuration of FIGS. 1 and 2 in that instead of the reference voltage source 207, the average peak value detecting means 30 for detecting the average peak value of the demodulated output signal of the demodulating means 101.
1 is provided, and as the average peak value detection means 301, an absolute value circuit 302 that outputs an absolute value voltage centered on the bias voltage of the input signal, and from the input of the reset signal until the input of the next reset signal Maximum value holding circuit 303 that holds and outputs the maximum value of the input signal between and the sample hold that holds and outputs the input signal at the time when the reset signal is input until the next reset signal is input Circuit 304
An integrating circuit 305 for averaging the input signal over a sufficiently long time, and a reset timer 306 for outputting a reset signal at a time interval which is, for example, four times or more as long as the transmission time of one symbol of the multi-level FSK signal 100. The point is that the sample hold circuit 304 is provided with a delay circuit 307 that delays the reset signal by the time required for sampling.

In the multi-valued FSK receiver configured as described above, the parts that operate differently from those in FIGS. 1 and 2 will be described below.

The absolute value circuit 302 supplies an absolute value voltage centered on the bias voltage of the demodulation output signal output from the demodulation means 101 to the maximum value holding circuit 303. Reset timer 306
Outputs a reset signal at an interval sufficiently longer than one symbol of the FSK signal 100, is supplied to the sample hold circuit 304 on the one hand, and is delayed by a delay time by the delay circuit 307 on the other hand, and then the maximum value holding circuit Supplied to 303.

The maximum value holding circuit 303 holds the maximum value of the output signal of the absolute value circuit 302 between the input of the reset signal delayed by a minute time and the input of the next reset signal, and sample-hold. Supply to circuit 304. Here, since the interval of the reset signal is sufficiently long with respect to the transmission time of one symbol of the FSK signal, if the bit data of the FSK signal appears uniformly, immediately before the next reset signal is input. , The maximum value of the demodulation output signal will be detected.

In the sample hold circuit 304, the reset signal is input a minute time before the reset signal is supplied to the maximum value holding circuit 303, and the output voltage of the maximum value holding circuit 303 is input to the next reset signal. Holds until the output and outputs. The average value of the peak values of the demodulation output signal is detected by averaging the output signal by the integrating circuit 305 over a sufficiently long time, and the average value is supplied to the threshold setting means 105. The threshold setting means 105 sets a threshold voltage according to the transmission speed information 108 using the output voltage of the integrating circuit 305 as a reference voltage.

As described above, according to this embodiment, the multi-valued FS is
When setting the threshold voltage according to the transmission speed of the K signal 100, by setting the threshold voltage relatively using the average peak value voltage of the demodulation output signal as a reference voltage, S /
The threshold value can be set in accordance with the decrease in the average peak value voltage of the demodulation output signal due to the deterioration of N, and the reception sensitivity can be improved.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram of the essential parts of a multilevel FSK receiver according to the third embodiment of the present invention.

4 is different from the configuration shown in FIGS. 1 and 2 in that the threshold value setting means 105 is provided with a memory 401 which stores in advance a digital value corresponding to an optimum threshold value according to the transmission rate. , The optimum threshold digital value is read from the memory 401 based on the input transmission rate information, the threshold voltage is calculated based on the output voltage of the reference voltage source 207, and the digital value is output. means
402 and D / which converts a digital signal into an analog signal
The configuration is composed of an A conversion circuit 403, and other configurations are similar to those in FIGS. 1 and 2.

In the multi-valued FSK receiver configured as described above, the parts that operate differently from those in FIGS. 1 and 2 will be described below.

A digital value corresponding to an optimum threshold value corresponding to the transmission rate of the multi-valued FSK signal 100 is stored in advance in the memory 401, and the threshold value calculation means 402 uses the transmission rate information extraction means 104. The optimum threshold digital value is read from the memory 401 in accordance with the supplied transmission rate information 108. Then, with the reference voltage supplied from the reference voltage source 207 as a reference, the digital value of the optimum threshold voltage is calculated and supplied to the D / A conversion circuit 403. D /
The A conversion circuit 403 converts the supplied optimum threshold digital value into an analog voltage and supplies the analog voltage to the bit determination means 102.

As described above, according to this embodiment, the multi-valued FS
The optimum threshold value corresponding to the transmission speed of the K signal 100 is stored in the memory 401 in advance, and the memory 4 is stored according to the transmission speed.
By changing the threshold voltage by reading from 01, converting to analog voltage and supplying it to the bit determining means 102,
It is possible to improve the reception sensitivity.

Although the reference voltage source 207 is used in this embodiment, the present invention is not limited to this.
Instead of 207, the average peak value detecting means 301 shown in FIG. 3 may be used.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram of the essential parts of a multilevel FSK receiver according to the fourth embodiment of the present invention.

5 is different from the configuration of FIG. 4 in that
The reception level calculation means 501 for calculating and outputting the reception level of the multi-level FSK signal 100 received by the demodulation means 101 is provided,
Instead of the memory 401, a memory 502 which stores in advance a digital value corresponding to the optimum threshold value according to the transmission rate and the reception level of the multilevel FSK signal is provided, and instead of the threshold value calculation means 402, the transmission value is transmitted. A threshold value for reading the digital value corresponding to the optimum threshold value based on the speed information and the reception level calculation result from the memory 501, calculating the threshold voltage based on the output voltage of the reference voltage source 207, and outputting the digital value. A value calculating means 503 is provided, and other configurations are the same as those in FIG.

In the multi-valued FSK receiver configured as described above, the part that operates differently from FIG. 4 will be described below.

The memory 502 stores in advance a digital value of an optimum threshold value based on the two parameters of the transmission rate and the reception level of the multilevel FSK signal 100.
The threshold value calculation means 503 calculates the transmission rate information 108 of the multi-level FSK signal 100 supplied from the transmission rate information extraction means 104 and the reception level calculation result of the multi-level FSK signal 100 supplied from the reception level calculation means 501. Based on this, the optimum threshold digital value corresponding to that case is read from the memory 502.
Then, the threshold voltage is calculated based on the reference voltage supplied from the reference voltage source 207, and the corresponding digital value is D
It is supplied to the / A conversion circuit 403.

As described above, according to this embodiment, the multi-valued FS is
In addition to the transmission rate information of the K signal 100, by adding the calculation result of the reception level to the judgment material of the threshold value setting, it becomes possible to set a more optimum bit judgment threshold value and improve the reception sensitivity. And

Although the reference voltage source 207 is used in this embodiment, the present invention is not limited to this.
Instead of 207, the average peak value detecting means 301 shown in FIG. 3 may be used.

(Embodiment 5) A fifth embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram of the essential parts of a multilevel FSK receiver according to the fifth embodiment of the present invention.

6 is different from the configuration shown in FIGS. 1 and 2 in that the multi-valued FSK signal 100 is changed to a 4-valued FSK signal 600 including redundant error correction information, and the bit data judged to be bit data is determined as the decoder 103. Error correction means 601 for performing error correction using the error correction information and outputting the bit data after error correction and the data of the error-corrected bit.
And an information extraction unit 602 that extracts and outputs the control information 106 and the transmission information 107 from the error-corrected bit data and the error-corrected bit data and the error-corrected bit data. BER calculation means 603 for calculating the bit error rate (BER) for each symbol of the signal 600 is provided, and instead of the threshold value setting means 105, the transmission rate information 108
And threshold value setting means 604 for outputting a threshold voltage for bit determination using the calculation result of the BER calculation means 603.
The other configuration is the same as in FIGS. 1 and 2.

In the multi-valued FSK receiver configured as described above, the parts that operate differently from those in FIGS. 1 and 2 will be described below.

First, the bit data which has been subjected to the bit determination by the bit determination means 102 is the error correction means 6 of the decoder 103.
01, and perform error correction using the error correction information,
The error-corrected bit data 605 and the position information 606 of the error-corrected bit data are output. Information extraction means 6
In 02, the control information 106 and the transmission information 107 are extracted from the error-corrected bit data 605 supplied from the error correction means 601 and output.

In the BER calculation means 603, the error correction means 601
The error-corrected bit data 605 and the position information 606 of the error-corrected bit data output from are input, and the BER for each symbol of the 4-level FSK signal 600 is calculated, for example, as shown in FIG. .

In the threshold setting means 604, the transmission rate information 1
The threshold is set based on 08, but the BER calculation means
When the BER calculated for each symbol is biased, the set threshold voltage is slightly changed so that the BER for each symbol becomes uniform. When the bit determination means 102 has the configuration as shown in FIG. 2 and the calculation result of the BER distribution is as shown in FIG. 7B, the frequency shift " f
The BER of the symbol corresponding to "2" is reduced, and the BER of each symbol is made uniform.

As described above, according to this embodiment, the 4-value FS
In addition to the transmission rate information of the K signal 600, B for each symbol
By minutely changing the threshold voltage so that the bias of the ER becomes uniform, the receiving sensitivity can be improved in the following cases.

As for error correction, as shown in FIG. 7 (c), 4-valued FSK
When error correction is performed by dividing the high-order bit (MSB) and the low-order bit (LSB) of 2-bit data corresponding to a signal, if bit errors concentrate on one side, there is a possibility that error correction will be impossible. Therefore, by making the bit error rate uniform for each symbol, it is possible to increase the probability of error correction and improve the reception sensitivity.

In this embodiment, the four-level FSK signal 600
However, the present invention is not limited to this, but multi-valued FS
It may be a K signal.

Further, in this embodiment, BE for each symbol is
Although the threshold value is constantly changed minutely based on the calculation result of R, the present invention is not limited to this. For example, when the calculation result of the BER for each symbol is extremely small, or the error correction means 601 does not correct the error. If possible, or if there is a large deviation in the appearance frequency of each symbol when calculating the BER, the threshold setting means 604
The control means may be provided to supply a control signal for stopping the minute change of the threshold value.

(Embodiment 6) A sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a block diagram of the essential parts of a multilevel FSK receiver according to the sixth embodiment of the present invention.

In FIG. 8, reference numeral 600 is a multi-level FSK signal loaded with error correction information, 101 is demodulation means similar to that in FIG.
01 is an A / D conversion circuit that converts the input analog signal into a digital signal, and 802 is a digital signal output from the A / D conversion circuit 801 that is bit-synchronized with the demodulation output signal and outputs a timing signal. Digital bit synchronizing means 803 makes a bit decision on the digital value of the demodulation output using a threshold value according to the timing signal, and outputs the digital decision value and the digital value of the demodulation output signal at the time of the bit decision. Judging means, 601 and 602 are error correcting means and information extracting means similar to those in FIG. 6, respectively, and 804 is a histogram calculating means for calculating the histogram of the value of the demodulated output signal at the time of judging the bit value for each symbol of the multi-level FSK signal , 805 is a threshold value setting procedure for setting the threshold value according to the transmission rate information 108 and the calculation result of the histogram of each symbol of the 4-level FSK signal 600. It is.

The operation of the 4-level FSK receiver configured as above will be described below. First, the 4-level FSK signal 600 is demodulated by the demodulation means 101, and the demodulated output signal is converted into a digital signal by the A / D conversion circuit 801. The converted digital demodulation output signal is supplied to the bit synchronizing means 802 and the threshold value judging means 803.

The digital bit synchronization means 802 establishes bit synchronization with the input digital demodulation output signal,
The timing signal 807 is supplied to the threshold value judging means 803. The threshold value judging means 803 compares the value of the digital demodulation output signal 806 with the threshold value set by the threshold value setting means 805 at the timing of the timing signal 807, and supplies the judgment result to the error correcting means 601. Further, the value of the digital demodulation output signal 806 at the time of determination is supplied to the histogram calculating means 804. Error correction means 601 and information extraction means
At 602, error correction and information extraction are performed as in FIG.

The histogram calculation means 804 uses the bit data 605 after error correction and the value of the digital demodulation output signal 806 at the time of bit judgment supplied from the threshold value judgment means for each symbol of the four-level FSK signal 600. A histogram of the values of the digital demodulation output signal 806 at the time of bit determination is calculated. The calculated histogram is, for example, as shown in FIG.
It will be as shown in (a).

The threshold value setting means 805 sets a threshold value according to the supplied transmission rate information 108 and supplies it to the threshold value judging means 803, and then each symbol calculated by the histogram calculating means 804. The threshold voltage is changed to a value at which each histogram intersects (value indicated by ∘ in FIG. 10A) and supplied to the threshold determination means 803.

As described above, according to this embodiment, in addition to setting the threshold voltage according to the transmission rate information, the histogram of the demodulated output signal at the time of bit determination is changed to the optimum threshold value. As a result, the optimum threshold value determination is performed, and the reception sensitivity can be improved.

In this embodiment, the four-valued FSK signal 600
However, the present invention is not limited to this, but multi-valued FS
It may be a K signal.

Further, in the present embodiment, the threshold value is always finely changed based on the calculation result of the histogram of each symbol of the four-level FSK signal. However, the present invention is not limited to this. For example, the error correction means 601. In the case where error correction is not possible, or when there is a large deviation in the frequency of appearance of each symbol when calculating the histogram, control for stopping the minute change of the threshold value in the threshold value setting means 805. A control means for supplying a signal may be provided.

[0067]

As described above, according to the present invention, the reception sensitivity is improved by detecting the transmission rate of the received multilevel FSK signal and changing the threshold voltage in the bit determination according to the transmission rate. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block connection diagram showing an essential part of a multilevel FSK receiver according to a first embodiment of the present invention.

FIG. 2 is a block connection diagram showing an application of the same embodiment.

FIG. 3 is a block diagram of the essential parts of a multilevel FSK receiver according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a main part of a multilevel FSK receiver according to a third embodiment of the present invention.

FIG. 5 is a block diagram of the essential parts of a multilevel FSK receiver according to a fourth embodiment of the present invention.

FIG. 6 is a block connection diagram of essential parts of a multilevel FSK receiver according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing an operating state of BER calculation means, which is a main part of the multi-level FSK receiver in the embodiment.

FIG. 8 is a block diagram of a main part of a multilevel FSK receiver according to a sixth embodiment of the present invention.

FIG. 9 is a block connection diagram of a main part of a conventional multilevel FSK receiver.

FIG. 10 is a diagram showing a frequency distribution of peak values of a demodulated output signal of a multilevel FSK receiver.

FIG. 11 is a diagram showing a frequency distribution of peak values of a demodulated output signal when the transmission rate of a multi-valued FSK signal is low.

[Explanation of symbols]

 101 demodulation means 102 bit determination means 103 decoder 104 transmission rate information extraction means 105, 604, 805 threshold value setting means 201, 302 absolute value circuit 202, 203 comparison circuit 204 bit synchronization circuit 205 latch circuit 206 bias voltage source 207 reference voltage Source 208 Voltage switching means 209 Switching control means 301 Average peak value detection means 303 Maximum value holding circuit 304 Sample hold circuit 305 Integration circuit 306 Reset timer 307 Delay circuit 401, 502 Memory 402, 503 Threshold value calculation means 403 D / A Conversion circuit 501 Reception level calculation means 601 Error correction means 602 Information extraction means 603 BER calculation means 801 A / D conversion circuit 802 Digital bit synchronization means 803 Digital threshold value judgment means 80 4 Histogram calculation means 901 Band pass filter 902 Oscillator 903 Mixer 904 Pulse count circuit 905 Low pass filter 906 Bit determination circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Katayama 4-3-1 Tsunashima-higashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.

Claims (12)

[Claims] 1. A multi-level FSK signal having a constant transmission rate section having a constant transmission rate for each predetermined time interval, and having the same transmission rate or a different transmission rate other than the constant transmission rate section, Demodulating based on transmission rate information, demodulating means for outputting a voltage proportional to the instantaneous frequency of the multi-level FSK signal, and demodulated output outputted from the demodulating means are bit-determined using a threshold voltage, A bit determining means for outputting the determined bit data; a decoder for extracting control information and transmission information according to a predetermined data format from the bit data output from the bit determining means; Transmission rate information extracting means for extracting the transmission rate information from the output control information and supplying it to the demodulating means; A first threshold value setting means for setting a threshold voltage for bit determination according to the transmission speed information output from the speed information extraction means and supplying the threshold voltage to the bit determination means. Characteristic multi-valued FS
K receiver. 2. A coupling circuit for removing an error voltage between a center voltage and a bias voltage of the demodulation output outputted from the demodulation means is provided at a subsequent stage of the demodulation means, and an output of the coupling circuit is a bit determination means. The multi-valued FSK receiver according to claim 1, wherein the multi-valued FSK receiver is supplied to the bit decision input of the. 3. A multi-valued FSK signal is a four-valued FSK signal, and a result of comparing a demodulation output output from the demodulation means with a bias voltage serving as a center voltage of the demodulation output is output as bit determination means. And a first comparison circuit for outputting an absolute value based on the bias voltage of the demodulation output.
An absolute value circuit, a second comparison circuit for outputting a result of comparing the output voltage of the first absolute value circuit with the threshold voltage supplied from the first threshold value setting means, and the second comparison circuit. According to the bit synchronization circuit that generates a timing signal by performing bit synchronization from the output signal of the first comparison circuit and the output signal of the second comparison circuit, and the timing signal generated by the bit synchronization circuit, 2. The multi-level FSK receiver according to claim 1, further comprising a latch circuit which refers to the output signal of the first comparison circuit and the output signal of the second comparison circuit and supplies it as bit data to the decoder. 4. The multi-valued FSK signal is a multi-valued FSK signal including error correction information. As a decoder, the error correction information is used for error correction of bit data, and the error-corrected bit data is output. A first error correction means and a first information extraction means for extracting control information and transmission information from the error-corrected bit data output from the first error correction means and outputting the extracted control information and bit information are provided. Unit and the first threshold value setting unit, an A / D conversion circuit for converting the demodulated output output from the demodulation unit into a digital value and outputting the digital value, and a digital signal output from the A / D conversion circuit. In accordance with the timing signal output from the digital bit synchronization means and a digital bit synchronization means for outputting a timing signal by bit synchronization with the demodulation output using Bit determination is performed on the digital signal output from the A / D conversion circuit using a threshold value, and the result of the bit determination is supplied to the first error correction means;
Further, by using the digital threshold value judging means for outputting the digital value at the time of the bit judgment, the digital value at the time of the bit judgment and the bit data after the error correction outputted from the digital threshold value judging means, Multi-valued FS
A histogram calculation means for calculating a histogram of digital values at the time of bit determination for each symbol of the K signal, and a digital corresponding to an optimum threshold value based on the histogram for each symbol calculated by the histogram calculation means. 2. The multi-valued FSK receiver according to claim 1, further comprising: second threshold value setting means for setting a value and supplying it to the digital threshold value judging means. 5. The multi-valued FSK signal is a multi-valued FSK signal containing error correction information. As a decoder, error correction is performed on the bit data output from the bit determination means by using the error correction information to generate an error. Second output of corrected bit data and position information of error-corrected bit data
Error correction means, second information extraction means for extracting and outputting control information and transmission information from the bit data after the error correction outputted from the second error correction means, and after the error correction. A bit error rate calculating means for calculating a bit error rate for each symbol of the multilevel FSK signal using bit data and position information of the error-corrected bit data; Instead of means, third
The threshold value setting means is provided, and the third threshold value setting means sets the threshold voltage according to the transmission rate information output from the transmission rate information extracting means.
If the bit error rate for each symbol calculated by the ER calculating means is biased, the set threshold voltage may be slightly changed to make the bit error rate for each symbol uniform. The multi-valued FSK receiver according to claim 1. 6. The bit error rate is calculated using the bit error rate calculation result by the bit error rate calculation means, the error-corrected bit data output from the error correction means, and the position information of the error-corrected bit data. When the calculation result of the bit error rate for each symbol by the calculation means is extremely small,
Alternatively, if the error correction by the error correction means is impossible, or if there is a large bias in the appearance frequency of each symbol when calculating the bit error rate, the third
6. The multivalued F according to claim 5, further comprising control means for supplying a control signal for stopping the minute change of the threshold value by said threshold value setting means to said third threshold value setting means.
SK receiver. 7. The first threshold value setting means includes a reference voltage source for outputting a reference voltage for setting a threshold voltage, and a reference voltage output from the reference voltage source as a reference. 4. The multi-valued FSK receiver according to claim 1, further comprising: fourth threshold value setting means for setting and outputting a threshold voltage. 8. As a fourth threshold value setting means, a plurality of voltages preset based on a reference voltage output from a reference voltage source are switched and output according to an input control signal, The voltage switching means supplied to the bit determining means and the switching control means for outputting a control signal for switching the output voltage of the voltage switching means according to the transmission speed information output from the transmission speed information extracting means are provided. A multi-valued FSK receiver according to claim 7, characterized in that 9. The peak value of the amplitude of the demodulation output of the demodulation means is detected instead of the reference voltage source, and the peak value of the peak value at a time sufficiently longer than the transmission time of one symbol of the multilevel FSK signal is detected. 8. The multi-valued FSK receiver according to claim 7, further comprising an average peak value detecting means for outputting the average voltage and supplying it as a reference voltage to the fourth threshold value setting means. 10. A second absolute value circuit as an average peak value detecting means for outputting an absolute value based on a bias voltage which is a center voltage of a demodulation output from the demodulating means, and after a reset signal is inputted. A maximum value holding circuit that holds and outputs the maximum value of the output signal of the second absolute value circuit until the next reset signal is input, and the maximum value holding at the time when the reset signal is input A sample and hold circuit for holding and outputting the output signal of the means until the next reset signal is input, an integrating circuit for averaging the output signal of the sample and hold circuit, and transmission of one symbol of the multilevel FSK signal. A reset timer that outputs a reset signal at a time interval that is four times longer than the time and a reset signal output from the reset timer are sampled in the sample hold circuit. A delay circuit for delaying the time required for the ring is provided, the output of the delay circuit is supplied to the reset input of the maximum value holding circuit, and the output of the reset timer is supplied to the reset input of the sample hold circuit. The multi-valued FS according to claim 9, wherein
K receiver. 11. A fourth memory as a fourth threshold value setting means, which stores in advance a digital value corresponding to an optimum threshold value corresponding to a transmission rate of a multi-level FSK signal, and transmission rate information extraction. According to the transmission speed information output from the means, the digital value of the corresponding threshold value is read from the first memory, the threshold voltage is calculated based on the output voltage of the reference voltage source, and the threshold voltage is calculated. And a D / A conversion circuit for converting the digital value of the threshold voltage output from the first threshold calculation means into an analog voltage. The output voltage of the D / A conversion circuit is supplied to the bit determination means as a threshold voltage.
The described multi-valued FSK receiver. 12. A reception level calculation means for calculating a reception level of a multi-valued FSK signal received by a demodulation means instead of the first threshold value calculation means and the first memory, and reception of the multi-valued FSK signal. A second memory in which a digital value of an optimum threshold value corresponding to the level and the transmission rate is stored in advance, and the reception level calculated by the reception level calculation means and the transmission rate output from the transmission rate information extraction means According to the information, the digital value corresponding to the optimum threshold value is read from the second memory, the threshold voltage is calculated with the output voltage of the reference voltage source as a reference, and the digital value of the threshold voltage is D / The multi-valued FSK receiver according to claim 11, further comprising a second threshold value calculation means for supplying to the A conversion circuit.